Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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pBlazSIM
I'm having a hell of a time getting started with the pBlazSIM and pBlazASM toolchain. Does anyone have a good resource?
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11 years ago
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Xilinx FIFO usage
It is my first time here, so hello everybody! :) I have problems with Xilinx FIFO on Spartan 3. As far as I understand it, standard FIFO sends data out in the next clock cycle after I set 'rd_en'...
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11 years ago
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USB power and debug signals on micro USB connector
For a handheld device, powered by a Li-ion cell, I need a charge power input. Most standard chips for charging and powering the device are meant for USB power or simular. Since the current standard...
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11 years ago
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FPGA DSP basics: clock enable / new clock
My current goal is to implement some digital signal processing (filters) on a FPGA. I am currently using Terasics DE0 nano board. This board has an ADC128S022 ADC. I have started as follows: From the...
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11 years ago
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DC fifo behaviour at underflow/overflow
We all know that a fifo should operate without getting empty or full. Does anybody have experience of what sort of output disorder can one expect when operating in the wrong state (underflow or...
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11 years ago
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MII SFD Detection with Shematics
Hello, I have to detect the Start of a Ethernet Frame. So I want to make use of a FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RX D 0-3, the Clocks, TX_EN and RX_DV). What...
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11 years ago
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Where to move for an embedded software engineer.
I assume the bay area is number one for embedded software engineers, but where else are the big markets, as companies run from califoria taxes. Denver, CO - Does big population mean high tech?...
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11 years ago
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Is this Multicycle?
Assume register r4 is driven by three registers r1, r2, r3 registers r1, r2, r3 drive out their data every 3 clocks, each on a different clock phase. r1 is driven successively in the order of r1,r2,r3...
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11 years ago
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Looking for evaluators for NEW Vector Processor for FPGAs, offers massive parallel performance, all programmable in C/C++
We are looking for testers/evaluators of our newly released MXP Matrix proc essor for Altera FPGAs (Xilinx very soon). This is a solution that enhances NIOS II(microblaze) processor by up to a 1000x...
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11 years ago
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How to transfer multiple bit data between phase shifted clock?
Hi All, I am designing a memory controller and I am using two clocks clk and clk_90. Phase difference between clk and clk_90 is 90 degree. I want to transfer multiple bit data between clk and clk_90....
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11 years ago
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USB Cable - RHEL 6.2 and ISE 13.3
Hello. I'm having trouble using the "Platform Cable USB II" with my new linux box. Basically, when I plug the USB cable into a windows box, the green light comes on, but if I plug it into the Linux...
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11 years ago
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V6 BUFR -> BUFG clocking structure (hold issue?)
Hi! I have a Xilinx webcase for about 2mo about this that goes nowhere ... may be better luck here. My problem: - V6 design - clocking structure with a IBUF to BUFR which drives a BUFG, so both...
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11 years ago
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VHDL expert puzzle
In the following link, a design is presented that alledgedly has a flaw. The claim is that this is a simple case and that any experienced designer will see the flaw immediately. (I don't.)
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11 years ago
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Set-up and hold times and metastability
Hi, I've been looking at synchronising data across clock domains, and have managed to confuse myself. Can someone confirm (or correct me) that the following is true. Metastability may occur if the...
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11 years ago
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Spartan 3A startup
So, after being assured Spartan 3A should be around for a while (Thanks, all who commented) I made a board for a Spartan XC3S50A in the 144 lead package. I am using an SST25VF010A serial SPI PROM for...
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11 years ago
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