Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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CFP - EuroMPI Workshop: PBio 2013 (proceedings published by ACM DL) + Special Issue in Journal PARCO (IF: 1.311, Q1)
Call for Papers --- EuroMPI Workshop: International Workshop on Parallelism in Bioinformatics ( proceedings published by ACM Digital Library) + Special Issue in the Journal Parallel Computing...
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11 years ago
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ModelSim version numbers
Does anyone know why ModelSim version numbers skipped from 6.6 to 10, missing out 7, 8,and 9? Thanks in anticipation. --------------------------------------- Posted through
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11 years ago
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OSERDES as delay regulator e.g. Artix 7
Dear all, as some of you know that the Artix 7 has no ODELAY so I can't handle my delays for the output. But there is a OSERDES as well with MMCM or the PLL to manage output pins with different phases...
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11 years ago
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platform cable usb II and efuses on spartan-6
has anyone managed to do anything with efuses on spartan-6? I expected to use an old parallel cable since I usually have much need for jtag, but efuses are only supported with platform cable usb II,...
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11 years ago
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Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea
Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea The Embedded System on Chip Lab of the Hallym University seeks to recruit p romising PhD...
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11 years ago
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Aldec Active-HDL - No Default Binding Errors
I'm getting some errors when I try to compile my design in Aldec's Active-H DL. # Warning: ELAB1_0026: : (79, 0): There is no default binding for component "buf". (No entity named "buf" was found). #...
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11 years ago
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arm cortex M0 ds and legacy spartan 3E 3A 3ADSP starter kits
hi folks, I am investigating for edu. purposes arm cortex M0 "design start edition" in legacy spartan3E1600 or 3adsp1800. Labs can't afford new boards this year... I am especially interrested in ddr...
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11 years ago
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Vivado - Pack I/O Registers?
Hello, Has anyone found the option in Vivado that controls I/O register packing? ISE has a single implementation option that forces the default to use the I/O registers on inputs and outputs where...
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11 years ago
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Idea Hunt, FPGA + ARM Cortex-M3
I aim to demonstrate the need for FPGAs as compared to MPUs like (e.g. ARM Cortex-M3 based from TI/ST) in doing processing intensive stuff. I am looki ng for some help in this regard. I want to show...
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11 years ago
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Using CAN on Zynq
Hello, might not be a real FPGA question, but I hope that some of you doing not only the hardware part but also working with the Xilinx SDK. I try to use the CAN controller on e ZedBoard under Linux....
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11 years ago
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Sometimes I Just Don't Get the Tools
I've learned to use Active HDL some time ago and never had too much trouble with it. But now it is not letting me use the waveform viewer in an effective way. I typically add all my signals once and...
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11 years ago
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ip core implementation on fpga
ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design. ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any...
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11 years ago
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JTAG, CONF_DONE failed to go high in device 1.
This is actually a re-post of my thread on ( ) Having got no answers I'll post here as well. Before anyone comments on this, I have searched the forum and read everything I have found on the internet...
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11 years ago
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implementation of 8051 ip core on fpga
i am getting these errors can anybody help!! ERROR:HDLCompilers:27 - "../../Documents and Settings/deepak/Desktop/8051/trunk/rtl/verilog/oc8051_alu_test.v" line 62 Illegal redeclaration of...
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11 years ago
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Re: i've used a verilog ip core of 8051...plz someone tell me what should i put in the "top module" feild provided..its showing error.plz its urgent someone help.
Absolutely nothing, because he mistook the title for the text. I'm not going to even attempt to read the post that you shoved into the title. Try writing a _short_, _descriptive_ title, like "8051...
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11 years ago
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