Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
xcv800 free design tools
HI I have an old Xilinx board called "XCV800" .So my question is: What is the xilinx software version that supports the programming and the bit stream implementation of this kind-XCV800- of FPGA...
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What a Xilinx fpga could do in 1988
I'm writing up a project that ran from 1988 to 1991. It involved building an ECL-based digital processor that ran at 25MHz, working into a couple of ECL SRAMs. Debugging the hardware was tedious and...
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Xilinx tools for XC3020???
I've got a 20-year-old Xilinx XC3020 development board. I think it would be fun to fire it up and bring it to the 20th anniversary FCCM in Seattle next month. ( I don't see XC3000-series supported on...
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pullup in Xilinx ISE 10.1
I tried building a small project in ISE 10.1 using the CoolRunner II CPLD XC2C128 and ran into a problem with pullups. I defined a few inputs with pullup in the UCF file, and the mapper complained...
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Inferring DSP48 PATTERNDETECT and ACIN/ACOUT cascade
I'm using Synplify and trying to infer some DSP designs into DSP48s. Somet imes it works well, but it's sporadic. I'd like the DSP48s to be cascaded using the ACOUT/ACIN dedicated paths, and sometimes...
 
ASIC prototyping question for Xilinx V7 2000
(1) I need to prototype Arm A5 processor in Xilinx V7 2000 FPGA. A5 has AX I bus and Xilinx supports DDR3 Controller+AXI bus using Core gen. Thus I c an actually use the DRAM with A5 in FPGA. The...
 
Using Quartus II without GUI
Dear All, Is there a tutorial for using Quartus II without the GUI? Ie. how to create a new project, how to configure PLL's, how to bind signals to physical pins etc? I have been writing Verilog code...
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The Raspberry Pi JTAG programmer
The Raspberry Pi JTAG programmer:
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Anybody got Microsemi/Actel Libero SoC 11.0 SP1 to work on linux?
Hi, Installation of 11.0Beta (the first complete download of Libero SoC 11.0) i s ok and runs. When downloading and applying the SPA patch or SP1 patch, li bero_bin exits with a missing symbol in a...
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Farnell increased price on Spartan 6
Price went from 17 EUR to 25 EUR Haven't checked other ICs, I'm only interested in this one. http://alturl.com/4dtfw
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EPROM programmer erase
(Sorry, this is a bit off topic, but I do use this to load bitfiles into FPGAs.) I have a Xeltek Superpro/Z eprom programmer, with their winsp ver. 1.0 software, running on Win 2K/Pro. Today I had...
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IP for SDIO serial port
I have been looking for an SDIO serial port. A single chip would work as well. SDIO async serial port Txd, Rxd, CTS, RTS Also Linux and Win drivers. Are these still around ?
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Xilinx XST and initializing block RAMs
Hi all, I'm using XST 14.2 and trying to use block RAMs to store constant data (i.e. as ROMs) for program code that will be run by a CPU. I want to infer the block RAMs during synthesis and then...
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Experience with Tektronix's FPGAview
Folks, Anyone can share their experience with the Tek's FPGAview? + Go ahead buy it + Wait for updates + Don't bother Thx. Sanjay
 
about the always block in verilog
always @(negedge nrst or posedge PCLK or negedge begin) begin ... end So,how can i determine what event does really happen in begin end block??
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