Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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problem with the GTX wrapper in questa
Hi, Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04. I am trying to simulate GTX wrapper (generated from xilinx coregen) in questasim. Steps followed by me : 1.Compliled the all...
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10 years ago
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A Question about FPGA IO Standard
hi, I have a custom designed board with spartan 2 (XC2S150) with some input data and clk line connected to a peripheral device, the clk level is 3.3V and FPGA IO standard(not defined in .ucf file so...
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10 years ago
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Mentor Graphics Precision RTL + LatticeECP3 Versa
Could I use the Precision RTL with the LatticeECP3 Versa development kit? LatticeSemi does provide a one year evaluation license (old version of the Diamond Design Suite) for this board. Any...
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10 years ago
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[ANN] XMODZ-Fast modulo reduction VHDL IPs
The XMODZ IP collection provides fast hardware implementations for the modulo computation on integers. The collection comprises of two distinct IP modules, modk for modulo by a fixed integer constant...
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10 years ago
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openCv and NiosII IDE
hi, Can I link libraries to a project using the Nios II IDE tools? I am using v9.0 and I want to link the OpenCV libraries to my project. it is related with cygwin or NiosII compiler? pleaze i need...
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10 years ago
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2013 International Conference on Field Programmable Technology (ICFPT2013), December 9-11, Kyoto Research Park, Japan, Call For Papers
--------------------------------------------------------------------------- ---- 2013 International Conference on Field Programmable Technology (ICFPT2013) December 9-11, Kyoto Research Park, Japan...
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10 years ago
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FPGA Board : Indirect SPI not working
I was able to make my own custom FPGA shield for an ARM Cortex M3 board (ar duino footprint ofcourse!). I used the PapilioOne as reference for basic bo ard design. There is no FT2232 on the board. I...
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10 years ago
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Cubic Spline Interpolator
This isn't a question; I'm putting this here as a reference so I can find i t in the future. This is how to build a cubic interpolator circuit that ta kes four samples and interpolates a sample...
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10 years ago
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Die size of BRAM/DSP48 in CLBs
Does anybody know how big a BRAM or DSP48 is in terms of CLBs? (In a Virtex 5/6/7 part.) I was wondering, in terms of die size, whether it's better to use a multiplier or, say, four 36-bit fabric...
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10 years ago
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XILINX Artix-7 DDR2-RAM-Controller
Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation of the simulation models from the MIG-tool. Only the top-level of the...
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10 years ago
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Linting tool setup
Greetings all, Further to previous thread(s), has anyone here experience in setting up a linting tool such as Spyglass or LEDA? How long did it take? My thoughts are that a suite of test-case files is...
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10 years ago
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Xilinx SDK 14.5 debug
I have a Microblaze design in SDK that I am trying to debug. I have an IP block with some registers that I can read and write. I have opened a new memory monitor window so I can see the registers...
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10 years ago
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The UK Device Developers' Conference - Last call
Hi, Just a final call, to say that we have a few places still available at each of the Conference locations. Although some workshops are now sold out, there are a few places still available on others....
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10 years ago
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Any experience of Equivalence Checking tools?
Greetings all, Has anyone hereabouts any experience with the use of Equivalence Checking tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro? Thanks in anticipation, Robert...
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10 years ago
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DEP function development on a low budget
Is it at all practical for home-builders on a very limited budget to develop DSP type functions, such as filters and the like, on FPGAs? Reading around, I get the impression that experimenters that do...
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10 years ago
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