Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: Low cost board with built-in USB for fast data transfer and lots of gates
When you say 'USB', are you intending to have a full USB stack on the board, so you can be an arbitrary USB endpoint (eg keyboard, mass storage, printer, camera)? Or will something like a USB-serial...
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10 years ago
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How to Use Spartan 6 Ethernet Port
Hi all I need your help.I met a problem when I use the SPARTAN-6 FPGA board (xc6slx45-csg324c).I'm currently working on a project that I need to send data from my PC to FPGA board using Ethernet port....
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10 years ago
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Free evaluation of HercuLeS high-level synthesis now available from Ajax Compilers, Inc.
Athens, Greece ? Jule 01, 2013 ? Ajax Compilers, Inc., (http://www.ajax announces the availability of a free evaluation version for its flagship product, the HercuLeS high-level synthesis environment....
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10 years ago
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Problems with Spartan6 CRC calculation
I am unsuccessfully trying to update Spartan6 CRC checksums after I make packet modifications. This is not a problem for Virtex/E/2/2P/4/5/6/7 or for Spartan3E, but Spartan6 is a different story...
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10 years ago
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USB Download Cable for Lattice Devices
I am looking to incorporate the download capability for the Lattice USB download cable into a design. I found an app note on this but it uses a slightly old chip the FT2232D. FTDI refers to this chip...
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10 years ago
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FPGA Exchange
I'd like to introduce a new FPGA discussion forum. It's called FPGA Exchange, and you can check it out at: Feel free to jump in, create new topics, or answer existing ones. Guy.
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10 years ago
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Pure HDL Xilinx Zynq Arm Instantiation
Hello All, I have a Xilinx Zynq development board and I am starting to teach myself to build systems for Zynq. The recommended flow described in UG873 is a very long sequence of graphical menu clicks,...
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10 years ago
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Equivalent .tdf file in Aldec Active-HDL?
Is there an equivalent .tdf file in Aldec Active-HDL? One can find "text design file" in Quartus II. I like the same in Active-HDL. Thanks.
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10 years ago
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comparing between Xilinx and altera
I have a project that need about 300KLE, I want to choose a device between the Xilinx V7 and Altera Stratix5, please give some suggestions, in the low -end devices,what is the key diffrence between...
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10 years ago
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Ask about finding maximum and second's maximum number in array is given.
I am starting to study VHDL. Now, I have to do an exercise with the following content: I have to define an array of 10 elements ( 8 bit range) ([3,4,2,8,9,0,1,5,7,6] for example). And 10 elements were...
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10 years ago
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Chasing Bugs in the Fog
I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it around I've concluded it must be in the FPGA code. I...
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10 years ago
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HBA tomorrow (Friday) 14th June
Hi Friday people, I won't be in on Friday - but Darren P. has kindly agreed to open up and operate Request Line. See you on the 21st, Alan
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10 years ago
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DDR2 Concurrent Auto Precharge
I have come across a VHDL Free Model Foundry mt47h16m16.vhd which gives me some errors. Has anyone else used this model? If so has anyone had issues with twr timing errors? Am I right in assuming that...
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10 years ago
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[ANN] LOOPGEN-Fast hardware looping VHDL IPs
The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants), namely: - HWLU, a...
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10 years ago
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New soft processor core paper publisher?
I have a general purpose soft processor core that I developed in verilog. The processor is unusual in that it uses four indexed LIFO stacks with expl icit stack pointer controls in the opcode. It is...
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10 years ago
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