Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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good SDC reference
Hello All, It has been many years since I used the Synopsys Design Constraint (SDC) la nguage to apply timing constraints to a logic design. Right now I am worki ng on a preexisting Altera Cyclone 4...
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10 years ago
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FPGA Synthesis to LUT: Looking for papers/algorithms
Hi, I am looking for some easy to understand papers/links that explain the mapp ing from a generic netlist to LUT. For e.g. looking at c=(a+b)*c - d; I w ould imagine there is a generic adder,...
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10 years ago
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timing closure
Hi everyone, I know the subject is a bit broad, but I'm having issues in achieving timing closure and I'm trying to add timing constraints but a bit randomly... Any pointer to a good source for a more...
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10 years ago
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Legal Issues Reproducing Old CPU
This might not be the best group to ask, but I figured I would start here. I need to duplicate a 35-year-old CPU. Are there legal ramifications doing this? For instance on OpenCores they have a...
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10 years ago
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Altera EP3CLS70U484C8N
Hi, Does anyone know where I can buy EP3CLS70U484C8N from the shelf ? I'm lookin for only 1 pcs. Best regards Adam
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10 years ago
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FPGA temperature measurement
We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage ring oscillator, followed by a divide-by-16 ripple counter, and brought that out....
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10 years ago
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Actel Designer Warning: CMP201: Net drives no load
Hi everyone, I have several ports of my design that are not driving anything and left 'open' on purpose, using the 'open' keyword in my component instantiation in vhdl. Now I receive loads of...
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10 years ago
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Call for Papers: International MultiConference of Engineers and Computer Scientists IMECS 2014
Call for Papers: International MultiConference of Engineers and Computer Sc ientists IMECS 2014 Draft Manuscript submission deadline: 8 December, 2013 Camera-Ready papers & registration deadline: 10...
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10 years ago
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Synthesis and mapping of ALU
Dear all, I have the following ALU code as part of a data path: -- purpose: simple ALU -- type : combinational -- inputs : a, b, op_sel -- outputs: y alu : PROCESS (a, b, op_sel) BEGIN -- PROCESS alu...
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10 years ago
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Problem in Xilinx xapp1052 DMA PCIE custom flow
Hi, I am using ML505 XC5VLX110t board for PCIe core implementation. To implemen t the xapp1052 DMA design for my Endpoint block plus, I am following a cust om flow. I copied my *.xst, *.xcf and *.scr...
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10 years ago
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Cascaded floating-point reduction?
y1= 1.5f*y0 - x*y0*y0*y0 ...Note that all quantities are in single precision floating point. I can't write this equation in behavioral form for synthesizer to optimize because it has to be broken down...
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10 years ago
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[HELP]problem with asynchronous fifo ip
Hi,all, I have some problem and I need help.I am using fifo ip core of spartan write clk is 125MHz.I set read enable read clk.But when I use 150MHz as the read clk, the data read from fifo is read...
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10 years ago
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Is a block spoof IP filter in hardware is required
IP TTL spoofed packet block in hardware I read recently, that some linux kernels have the ability to block spoofed packets. Some hackers attack servers by sending many packets. They also put some fake...
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10 years ago
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[cross-post] vlib, vmap, vcom, how it all works...
Hi everyone, I'm trying to understand the details of each individual step from my source code to a running a postlayout simulation with ModelSim. I've read several articles on what are the steps, I've...
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10 years ago
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Xilinx Xcell Journal 84--Xilinx Goes UltraScale
Hey folks, my team just published a new issue of Xcell Journal. The issue h as a cover story on UltraScale, which should shed a bit more light on the p roduct strategy (at least what we are revealing...
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10 years ago
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