Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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generating clocks
Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks of 15 0MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll core since it does not generate the exact clock. If i...
6
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10 years ago
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6 | |
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how does PC communicate with FPGA?
Hi, I am unable to understand that how a PC communicate with FPGA. I have used Xilinx software to implement codes and then connected a USB cable to Xilinx test kit that did all jobs for me. Of course...
2
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10 years ago
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built in adc in fpga????
hi guys, i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am...
6
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10 years ago
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6 | |
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Verilog module not working,binary division,shifting problem!!
Sorry for my poor english :/ I want to divide unsigned binary integers using non-restoring division! I have found te algorithm here: I have implemented the algorithm on verilog.But for some reason the...
4
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10 years ago
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4 | |
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Verilog Binary Division
I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is this one: module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a,b);...
15
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10 years ago
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15 | |
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FREE download of HercuLeS high-level synthesis!
Dear all, HercuLeS by Ajax Compilers, Inc. ( is an easy to use high-level synthesis (HLS) environment for the automatic translation of algorithms to hardware. HercuLeS is suitable for both...
3
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10 years ago
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3 | |
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microsemi technical support
Hi everyone, this might be a stupid question to ask here but I really do not know where else I can post it. I filed 4 technical support requests on the Microsemi website last Friday and, as of today,...
4
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10 years ago
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Implementation ingnoring custom IP made with HLS
Hello, I am not entirely sure if this an implementation problem or an HLS problem but i will try here first. I have a microblaze system alongside a custom IP that has memory interfaces for I/O made by...
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10 years ago
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Zynq devices, boards and suppliers
I'd like to pick people's brains about aspects of different *suppliers* of Zynq boards. Avnet and Digilent are front-runners, but any info/opinions about other suppliers would be helpful too. - ease...
24
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10 years ago
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24 | |
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Vivado HLS -> Vivado IDE -> Xilinx SDK toolflow integration issue
Hello all, I have been using Vivado HLS to create an IP to later use the rest of the t oolflow to implement a system using a Microblaze and the HLS IP. HLS actaul ly automatically creates drivers for...
1
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10 years ago
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extra reset pin should not be needed..
Do any of the vendors provide a way to use the global reset net, but avoid having to tie it to a pin. In other words: module top ( in, q ); wire clk; wire reset_l; internal_clock_generator osc...
5
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10 years ago
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reset strategy FPGA Igloo
Dear all, I fear that I have an issue with reset time propagation all over my design and this may cause unknown initial conditions after reset. We have a pll and we use the 'lock' signal as a global...
45
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10 years ago
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45 | |
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Book recommendation
Hi, I'm new on this group. I'm starting my final year's project and I'm building a "interpolated multi-axis controller" (aka NC controller). I will use a FPGA (probably an spartan 3) to build a DDS, a...
11
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10 years ago
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Granularity of components for FPGA synthesis?
Hello, I am busy designing a small microprocessor system, which I have partitioned into the data path, the micro-controller, the memory, a multiplexer for the data bus input and a couple of simple...
7
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10 years ago
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7 | |
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VTR 7.0 Release Announcement
To the FPGA Research Community, We are pleased to announce the release of VTR 7.0. VTR is an open source f ramework for FPGA CAD and architecture exploration. The framework includes CAD tools that map...
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10 years ago
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