Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Gowin - This Just Got Real
I've been watching the various FPGA startup companies and a couple have pro duct available through mainstream distributors. The one I like the most is Gowin because of the easy to use packages they...
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3 years ago
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Why am I getting different results with two files collapsed into one?
I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp , input rightOp); wire notRight, xorWeak; supply1 power; supply0...
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3 years ago
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Synthesizable open FPGA cores
Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing performance. Could you please point me to their repositories ?...
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3 years ago
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To Reset or not to Reset, That is the Question!
Whether tis nobler to suffer the slings and arrows of outrageous judgement or just add the pointless, incorrectly working async reset that every frigg in' text book and every training example shows....
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3 years ago
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Using DSP Units
I working with the Gowin GW1N devices and need to do some serious math. By serious, I mean a number of calculations, not that they have to be fast. In fact, I pretty much have all the time in the...
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3 years ago
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Programming a Traffic Light Controller In verilog using Quartus Prime Lite
Hi everyone, ( Don't know if this is even the right place to post a question but ill tr y my luck) So basically I am a student and I have a final project to build a traffic l ight control system using...
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3 years ago
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Finally! I figgured it out accidentally.
Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the Active-HDL source directory buried down in the bowels of...
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3 years ago
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Is there a way in Verilog to refer to a slice of an array?
I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [...
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3 years ago
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ready/valid vs 2-way handshaking vs 4-way handshaking
I am confused about whether ready/valid handshaking is functionally equival ent to req/ack (2-way) handshaking? By being functionally equivalent, I mea n that we can perform data transfers with...
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3 years ago
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HP "owning" the software for Xilinx-FTDI drivers???
Someone new on the project is talking about how HP owns the driver code for the FTDI JTAG chip used to program Xilinx parts. Has anyone heard of this ? Even if that is true, I'm not sure how relevant...
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3 years ago
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Active-HDL Throws Error
My code is assigning an incremented unsigned value to an aggregate so the s um and carry can be extracted without duplicating logic or excessive lines of code (VHDL can be verbose we all know). But it...
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3 years ago
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Gowin Synthesis Software
Just had my first taste of the company supplied software from Gowin Semicon ductor. It's ok. Documentation is terrible being not much more than a lis ting of the menu items. Lots of features are...
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3 years ago
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XLNX on the Auction Block?
I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up from last week's close of $105.99. Other than the company name on documentation...
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3 years ago
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adding FPGA grounds
One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce ground impedance and add some damping. Has anyone done this? Does it...
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3 years ago
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Real Time Simulation
I'm working on a project with a number of non-EE, non-CE types. A CE mocke d up a real time simulation of the UI which will be done in the FPGA. I am writing the HDL which everyone is nervous about...
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3 years ago
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