Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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full functional coverage
Hi everyone, I'm trying to understand how to improve our verification flow. As of now we have a great deal of unit level testbenches which are trying to make sure the unit is behaving correctly. Now,...
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10 years ago
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cloud design flow
Hi there, I was wondering if there's any one out there working with a cloud design flow which is tool agnostic. The reason for asking is that I'm trying to evaluate if there's a way to integrate the...
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10 years ago
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license server
Hi everyone, is there any license server out there providing licenses on a 'per-use' base? we have several licenses in house, mostly node-locked, some floating but in our FPGA design flow a great deal...
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10 years ago
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[ANN] Availability for remote task/assignment work
Dear all, I hope you are doing well! I would like to let you know that I'm actively seeking for collaboration opportunities, such as permanent work, contract work or (remote or on-site) project/task...
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10 years ago
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Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
Hi folks, Professor Wirth, some may know his name as the inventor of Pascal and Oberon etc., has published recently, together with Jürg Gutknecht and Paul Reed, an exciting project at: Its a complete...
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10 years ago
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FLASH on MachXO2/3
Part of MachXO2 attraction for me was in internal, user accessible FLASH. I thought that I could use it for program of some small CPU I could build. But as far as I can tell, accessing this FLASH is...
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10 years ago
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New Lattice FPGAs on 40nm ?
I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to come out I wonder what happened to ECP4. As I understand it, Lattice found its market niche in...
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10 years ago
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micro blaze
Hi all how can we run a set of instructions (application) with Micro Blaz.
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10 years ago
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How to implement Ethernet packet classification with vhdl on FPGA? does any one has vhdl code or reference? Thank you.
I'm working on implement the basic ethernet switch on FPGA. But I don't kno w how to parse packet when they enter to switch. I have already used ip cor e (Ethernet MAC and fifo )to receive and...
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10 years ago
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Online Hardware Design Competition: Kode Da Circuit
Felicity '14, brings brings to you one of it's kind, Online VHDL Coding Competition, Kode Da Circuit. In this contest, participants have to come up with hardware solution for given problems which will...
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10 years ago
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How to find power supply pins in Lattice Diamond projects
I have a Mach02 demo board and am driving it with Lattice Diamond. With some searching I found io pin list of the device, but there are no power supply pins in that list. Probably something else is...
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10 years ago
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Call for Papers: 3rd International Conference on E-Learning and E-Technologies in Education ICEEE 2014
The Third International Conference on E-Learning and E-Technologies in Educ ation (ICEEE2014) March 18-20, 2014 Asia Pacific University of Technology and Innovation (APU) Kuala Lumpur, Malaysia The...
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10 years ago
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How to synchronize register bank used in the IP Core
Hello, I have designed an IP Core and I am using some registers to control Microprocessor writes into these register and IP Core reads these question is which is the best way to provide...
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10 years ago
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Submit articles now! 4th Conference on Digital Information Processing and Communications - MALAYSIA
The Fourth International Conference on Digital Information Processing and Communications (ICDIPC2014) Asia Pacific University of Technology and Innovation (APU), Kuala Lumpur, Malaysia March 18-20,...
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10 years ago
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Invitation: ICEEE2014 Kuala Lumpur, Malaysia
You are invited to participate in: The Third International Conference on E-Learning and E-Technologies in Educ ation (ICEEE2014) that will be held at Asia Pacific University of Technolog y and...
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10 years ago
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