Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Simulation deltas
Hi, This question deals both with an actual problem, and with some more concept ual thoughts on simulation deltas and how an RTL entity should behave with regards to this. This post regards the case...
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10 years ago
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Any good reference works on serial buses?
Hi all, I would like to understand and experiment with serial buses and protocols inside an FPGA (like AXI). Is there any reference work that you can recommend? Regards, Jurgen
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10 years ago
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ip address of fpga
what is an ip addres of fpga... my staff hav given me paper regarding security for ip address of fpga using watermarking in look up table... but i cant understandmuch about it since i lack basics on...
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10 years ago
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Sending and receiving of 10GBASE-R Ethernet frames via GTX transceivers in FPGA?
Hi, I'm working on a code which is supposed to send and receive 10GBASE-R Ethernet frames via SFP+ modules connected to the GTX transceiver in a Kintex-7 FPGA. I've read the section 4 of 802.3-2012...
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10 years ago
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Lattice MachXO3L - is it available anywhere ?
I've downloaded documetnation on lower part of newcomers - MachXO3. New Diamnond 3.1 has support for chips, but I can't find chips anyhwere. I tried Farnell and Mouser and couple of other adresses,...
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10 years ago
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lattice Diamond on Linux - programming doesn't work...
I've managed to manually install Diamond ( latest 3.1 64-bit) on my Gentoo. Now everything seems to be working, except programming the chip on board. I am playing with their MachXO2 breakout board and...
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10 years ago
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[cross-post][long] svn workflow for fpga development
Hi everyone, this is not really a question, but more some food for thoughts on how to optimize an fpga development flow leveraging the benefit of a vcs. I've been using svn since sometime now and I...
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10 years ago
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looking for a basic PCIe example
Hi, I'm looking for a high-speed PCI express example, like the one given in this video: but obviously my google-fu is failing me because I can't find an example matching the video. Does anyone have a...
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10 years ago
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debug access to memory (JTAG?)
Hi, I'm looking for a vendor-independent solution to configure RAM contents on an FPGA without rebuilding the RTL. Is there such a thing? Xilinx has their proprietary data2mem interface that let me...
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10 years ago
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Xilinx ISERDESE2 deserializer primitive behaviour
Hi, I'm having some problems to understand the exact behavior of the ISERDESE2 primitive. What I need to understand is exactly how the unit will distribut e the serial input to the bits in the output...
8
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10 years ago
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license issue on synplify pro AE
hy everyone, we have a floating license for Libero IDE which has an ACTEL_SUMMIT feature that to my understanding should support the whole project flow, including license for ModelSim AE and Synplify...
4
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10 years ago
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data read write to DDR2 SDRAM memory between microblaze and custom IP using PLB Bus
Hi everybody, I implement an xps system by using the Bus PLB. My IP core is added to the system using Create or Import Peripheral... I want to know how can Microblaze write several data to DDR2 SDRAM...
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10 years ago
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[cross-post]path verification
Dear all, I have a microcontroller with an FPU which is delivered as an IP (I mean the FPU). In order to run at a decent frequency, some of the operations are allowed to complete in within a certain...
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10 years ago
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CoreABC from Microsemi
Hi everyone, I'm currently laying down the architecture of an FPGA which is the main controller for a set of mechanisms and we wanted to profit of an amba ahb to interconnect various elements [1],...
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10 years ago
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how add an IP on vivado for Nexys4
hello i have Nexys4 Board (Artix7) and i want to add an IP to microblaze can you help me?
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10 years ago
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