Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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MachXO primary clock example (PCLK)
Hi! I'd like to use an external 25MHz TCXO as a primary clock. Unfortunately, t he application notes (at least what I've found) are very laconic on this to pic. The only examples are of the OSCC...
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9 years ago
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22V10 programmer
Does anyone know of a cheap 22V10 programmer ? or maybe a Atmel ATFxxxx programmer ?
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9 years ago
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HELP: Edge triggering of mode register, Verilog
I'm a relative Verilog noob, and stuck on the following, not sure if I'm structuring the problem wrongly or if it's just a case of bad coding. BTW, this is not homework, I'm 40 years too old to be...
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9 years ago
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Access custom VHDL types in TCL script
Hi Guys, I'm having a custom type in VHDL: type alu_op_code is ( ALU_OP_IDLE, ... ); Now having a testbench written in TCL i wawnt to force signals of type alu_op_code. How to actually do that? For...
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9 years ago
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Ethernet Switch on Configurable Logic now available
Now available from our repository a highly configurable Ethernet Switch for FPGA implementations. Check for more details.
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9 years ago
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Job - Promotion - 2D/3D Bildverarbeitug - FPGA
Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folgenden...
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9 years ago
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who that have used xfuzzy create vhdl ip to edk build gpio ip?
Recently i used the xfuzzy software create vhdl code. It was created vhdl code that used to xilinx edk add new project. and i search some information or literatures. It show GPIO and hardware BUS...
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9 years ago
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ECG signals Compression/Decompression
Hi, I want to ask you if it's feasible to create an ECG compression/decompression algorithm using decomposition of the ECG signal into orthogonal polynomials bases on FPGA. And if it's possible, do...
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9 years ago
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shift register (invariable size) FIFO = ?
Hi, if I chain up a bunch or registers (or use shift registers), the data comes out only after it has passed through the whole memory length. Even though "first in" comes out first, at least [1]...
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9 years ago
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Trigger implementation on ADC-FPGA
Hi, I'm trying to implement hardware trigger functionality by modifying the FPG A code for the LM97600RB from Texas Instruments which uses a Virtex-5 FPGA, and then implementing it on our custom board...
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9 years ago
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FSL Bus Problem
Hi everybody, I have connected a coprocessor to Microblaze in EDK through FSL. My problem is when i read data from FSL Bus; I do not get data from my ip from fsl. I want to know how can I simulate the...
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9 years ago
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integrate microblaze in ISE and VHDL code
Dear all, I'm beginner to use microblaze. I made a simple program to read two numbers from uart and add them using microblaze. For further purposes I want to integrate the microblaze as subcomponnet...
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9 years ago
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Re: Microblaze and MBLite
[] [] you'd need to find bridges to a commonly supported bus. IIRC on opencores there are bridges from/to wishbone/amba. The rationale behind the MBlite is to provide a platform which is 'lite' w.r.t....
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9 years ago
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Signal Integrity Failure on Custom FPGA board
Hi I have just gotten a custom FPGA board in house and I am having trouble programming it. The FPGA I am using the Actel(Microsemi) Igloo AGL250V2-FGG1441 There is a 10 pin JTAG header on the board....
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9 years ago
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How to reduce "Core static thermal dissipation" from fpga design in Quartus
Hello sirs, I'm working on this problem for some days, and I'll be grateful if anyone c ould help. I have a fpga cyclone II design and I need analyze its power consumption. My problem is: In these...
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9 years ago
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