Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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wishbone bus between two fpgas
Hi everyone, we are in the preliminary phase of the architecture definition for our system and we estimated FPGA resources (for a particular target) to be ~80% of the target's capabilities. Being at...
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9 years ago
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ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit Linux version) ?
I have downloaded latest Diamond and installed it on my Gentoo OS. It works normally except that I can't choose ECP5 part, because program lists none. I can see MachXO3L series, but no ECP5. BTW, I do...
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9 years ago
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What use of Python, Perl in FPGA development?
Hi, I often see some FPGA positions requiring Python, Perl. What use of these scripting language? I know TCL used in FPGA tool chain. I am very curious about it? Thanks,
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9 years ago
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FT2232H synchronuous FIFO mode problem.
Hello, I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA via FT2232H in FT245 synchronuous FIFO mode works perfect. However, I've g ot some problems with reading from FPGA to...
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9 years ago
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[cross-post] dither generator on fpga
Hi there, we are measuring from a quadrature encoder the raw sine and cosine and need to extract the angular position [1]. The position is then fedback to a PID which drives a motor. We've been told...
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9 years ago
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A free VHDL simulator
Hi, before downloading ISE webpack, I wanted to ask, if there is a free VHDL simulator, which is easy to compile or stable ? FreeHDL crashes on my machine, and ghdl -> I don't know how to compile. Any...
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9 years ago
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Need help for freehdl
Hi, can gvhdl compiled .o files interface with a c-program ? I would like to implement some mathematical function in VHDL and call this function with some input and retrieve the output. Additionally...
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9 years ago
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A new domain for FPGAs ? Function approximation
Hi, I don't know, what is state-of-the-art for function approximation on FPGAs. I developed this : "Paper" (10 minutes hack) for this : If I tried to implement the constructor for PBFs in VHDL, like a...
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9 years ago
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Open source Verilog BCH encoder/decoder
As part of my research, I needed a BCH encoder/decoder engine. Sadly, such a thing has no existed under a permissive license. Even more depressing is that many students seem to submit Verilog or VHDL...
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9 years ago
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problem with xc3s400 place and rout section
hi i have a custom designed board with xilinx spartan 3( xc3s400 ) with two ethernet phy layer (RTL8201) for a two port switch. I have a ring network of 10 of this board on the chain. i transmit data...
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9 years ago
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PLB to AMBA AHB bus bridge
Hi everybody, I want to know if there is an opensource PLB to AMBA AHB Bridge? Thanks. regards,
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9 years ago
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[OT] 2 full-time openings at Xilinx (embedded systems, embedded software, SoC, FPGA)
Hello, Xilinx (San Jose, California) has 2 full-time openings for people intereste d in software development, embedded systems, SoC chips, ARM architecture an d FPGAs. Ideal candidate would love...
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9 years ago
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NAND flash interface through FPGA
i want to interfacing NAND FlASH through can help me?
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9 years ago
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Call for Papers: International Conference on Education Technologies and Computers ICETC2014
The International Conference on Education Technologies and Computers (ICETC 2014) Lodz University of Technology, Lodz, Poland September 22-24, 2014 The conference aims to enable researchers build...
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9 years ago
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Need help to provide input/output timing constraint for DDR Interface
Hi All, I am working on SD Card IP Core for Altera FPGA which has DDR and Output Timing requirements for SD Card is given below tISUddr (Input Setup Time) = 2.5ns, tIHddr (Input Hold Time) = 2.5ns,...
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9 years ago
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