Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Name this pipelining technique
Hi, I vaguely recall reading papers that described an automated pipelining technique that could take an existing synchronous design and turn it into a N-way hyperthreaded design by replacing all the...
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9 years ago
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Timing Constraints: are there any "design patterns" indicating good practice?
I'll shortly be starting a design in a Zynq FPGA using Vivado. I'm confident that I will be able to use VHDL to create the design, partly because it isn't outside my comfort zone, and partly because...
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9 years ago
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Image rotation
Hello, I've come up with an issue, where I need to rotate the incoming video stream image by +/-5 degrees with 0.5 degree step. The problem now is to identify the most resource saving approach, which...
4
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9 years ago
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4 | |
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Parallel execution of Systemc code
// Testbench rst=true; wait(10, SC_MS); rst=false; in1=8; in2=2; in3=3; in4=6; sel=2; wait(50, SC_MS); cout
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9 years ago
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9 | |
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Prime number in verilog
Please any one give me the idea how i can generate prime number in verilog without the use of for loop. i computed in this way that a prime number is not divisible by its previous prime number.
6
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9 years ago
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How to automatically allocate multiple bit fields into constant length registers?
Hi, I have to implement control interface in an FPGA connected to the bus with certain width of data bus (let's assume, that it is 32 bits wide). In the c ontrol interface I have to implement some...
12
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9 years ago
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12 | |
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Monitor connections
Is there a way to monitor signals in existing wires? For example, with an oscilloscope and probe I can watch voltage changes. Is there a standard way to connect to an existing, working device, and...
7
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9 years ago
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Using FPGA to feed 80386
Would it be possible to connect an FPGA up to an 80386 (or other) CPU, to respond to memory and port requests, and leverage it as a resource? I'm thinking software runs on the 80386, given it by the...
85
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9 years ago
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Re: Problems with Xilinx SDK and LwIP
This is an old thread, but I had the same errors. Turns out I didn't have the hardware configured correctly. When I finally did a clean build on my project, the BSP didn't compile and threw an error...
1
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9 years ago
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1 | |
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VHDL Synchronization- two stage FF on all inputs?
Hello, I know this topic is beaten to death but I am a bit unlcear some things. I've recently encountered metastability issues that caused my FPGA to do unpredictable things. Someone suggested that I...
38
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9 years ago
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38 | |
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ICE40 Logic Cells
I was aware that the ICE40 devices have some limitations compared to other devices that are not so cost and power constrained. Until now the apparent lack of LUT RAM escaped me. I guess it is one of...
2
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9 years ago
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Which Altera to buy?
Greetings. I am new to FPGA programming. I am seeking to create a 40-bit 80386-like CPU core with a 32-bit and 64-bit FPU with 16 registers, a 128-bit four- and two-way 32-bit and 64-bit vector FPU...
68
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9 years ago
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68 | |
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FPGA on Android
- non-volatile FPGA plus FTDI USB chip - connects to an Android host mode USB port - application software in Lua, with Java interface/driver - high-level Gideros software for whizzy graphics - FPGA...
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9 years ago
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Low-end FPGA mezzanine standard
Anyone know if there's a standard(ish) for simple mezzanine cards for FPGA boards? I know about things like FMC and HSMC which are very 'high end' - multi gigabit transceivers, expensive connectors....
21
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9 years ago
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FYP Selection!
I have to choose a project for FYP from these three topics: I am confused b etween these three topics. My aim after Bachelors is to go for MS in VLSI. Which will be best for help ing me in MS?...
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9 years ago
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