Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
PCIe card with FPGA and DAC
I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be done with a PCIe PC-plugin board that has an FPGA and a fast...
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Open/Free HLS weapon of choice ?
Hello all, I would like to know which open or free HLS (High Level Synthesi s) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the...
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hands on experience on SystemC
Hi everyone, I'm cross-posting here from the SystemC Accellera Forum since I believe I'm likely going to receive more feedback here than there. I've recently started to wonder what kind of project I...
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Is it possible to have a parameterized verilog module name in verilog or systemverilog?
Hi, I am trying create verilog module that can support parameterized instance n ame. I understand that the signal width and other such things can be parame terized. But can we also parameterize the...
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[Call For Papers]: The 18th Conference on Reconfigurable Ubiquitous Computing, RUC'2015, Szczecin, Poland, Sep. 17 - 18, 2015
The 18th Conference on Reconfigurable Ubiquitous Computing, RUC?201 5 Szczecin, Poland, Sep. 17 - 18, 2015 Conference Information The 18th Conference on Reconfigurable Ubiquitous Computing is...
 
ESP8266 based Xilinx Virtual Cable server?
Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specification available: and when it is included in the newer versions of Vivado suite:...
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Oqpsk Demod
Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the difference between qpsk and oqpsk is only the delay of one bit period in q channel....
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IIR filter bus width
Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it should be more reliable on fixed point designs, as mine is. My input signal is...
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Clock triggered FSM
Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter...
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16->5 "Sort"
I'm trying to design a circuit (Virtex-7) which you might call either a pri ority encoder or a sorter. This is what it should do: Given a 16-bit vector with 5 bits set, create a list of 5 4-bit...
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ZYNQ temperature
Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do.
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Spartan-3 stater kit
Dear all, I'm really not a specialist in FPGA :-) For several years now I have a microbalze SoC running on a Digilent Spartan -3 Starter Kit Board with a XC3S200 FPGA. The board acts as the digital...
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Xilinx Aurora link splitter
Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devices A and B connected using Aurora link (single lane, full duplex) over SFP +...
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Directly connect two XAUI ports inside FPGA
Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6. Therefor we did instantiate two XAUI-cores and connected...
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