Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ML405 Xilinx ISE 14.7
Dear all first of all want thanx to everyone who belong to this forum and give help to each other. I checked ML405's schematic that pins, and are exist,i used advice of Aurelian Lazarut (cleaning...
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8 years ago
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Found: an FPGA with internal tri-states
In has been mentioned here a few times that there are no FPGAs with internal tristates. However, surfing around somewhat aimlessly, I stumbled upon a device series which has them and obviously had to...
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8 years ago
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Quad-Port BlockRAM in Virtex
I think I need a quad-port blockRAM in a Xilinx V7. Having multiple read p orts is no problem, but I need two read ports and two write ports. The two write ports is the problem. I can't double the...
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8 years ago
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DC Blocker
Hi all, I need to implement DC blocker in FPGA. Data samples are coming at every clock cycle. My original idea was to implement high pass filter as in formula below: y[n] = x[n] - x[n-1] + p*y[n-1]...
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8 years ago
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Interfacing ADS7230 ADC to Altera FPGA
Hi all, I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030)...
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8 years ago
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error Xst:899
I am receiving this error in xilinx ERROR:Xst:899 - "../../rtl/dff.v" line 7: The logic for does not match a known FF or Latch template. The code being synthesizd is: module dff(output reg qout, input...
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8 years ago
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Sum of 8 numbers in FPGA
How do I most efficiently add 8 numbers in FPGA? What is the best way to save LUTs? How is data width affecting LUT consumption? Thanks in advance. --------------------------------------- Posted...
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8 years ago
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recovery/removal timing
Hi All, In Altera devices (at least) it is recommended that reset be applied to the async port of flips. It is also recommended that such reset should be pre-synchronised before wiring it to these...
51
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8 years ago
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51 | |
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FPGA/HDL/HLS/Digital design centered Master degree online
Hi. I'm looking at universities that offer online/distance (part or full time) master degree based in FPGAs, HDLs/HLS and/or digital design. I wonder if someone knows of such a degree, or can point in...
2
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8 years ago
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Custom FPGA routing
1)Have an array of logic cells or programmable logic evenly spaced out. Need to have the space reserved for routing channel. 2)But each logic cell need some SRAM configuration bits from configuration...
2
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8 years ago
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System On Chip From Microsemi
I guess I stopped looking at the Microsemi products some time back. The SOC devices put out by Actel were ok, but the price was up there even for the smallest one, around $50. I was looking on Digikey...
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8 years ago
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DDR* SDRAM modules for simulation
Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for simulating a memory chip/module?? I want to build a memory...
6
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8 years ago
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Automatic latency balancing in VHDL-implemented complex pipelined systems
Hi, Last time I have spent a lot of time on development of quite complex high s peed data processing systems in FPGA. They all had pipeline architecture, a nd data were processed in parallel in...
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8 years ago
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Soft core processors: RISC versus stack/accumulator for equal FPGA resources
It would appear there are very similar resource needs for either RISC or Stack/Accumulator architectures when both are of the "load/store" classification. Herein, same multi-port LUT RAM for either...
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8 years ago
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Xilinx Spartan2E options?
I have a product series that has mostly moved to Spartan 3A, but one member of the family is still using up boards made some time ago with the Spartan2E. I just found a mistake in all of the designs...
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8 years ago
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