Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
How to get the area/time results without IO mapping
Hi all, I want to evaluate the area and time cost of an intermediate product on Xilinx FPGA. But the number of output ports exceed number of I/O pins. (Actually there will be much less outputs in the...
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Xilinx MIG DDR2 Documentation
I am trying to use the Xilinx Memory Interface Generator (MIG) version 1.6 to generate a DDR2 x16 core for initiall testing of a XC4VFX12-10SF363 board that we are bringing up this week. The memory is...
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MIG 1.6 on ISE-9.1i-SP1
Hi all, Does MIG1.6 work on ISE9.1i+SP1? I plan to implement a DDR2-SDRAM controller. Thanks in advance Mehdi.
 
ROC PORT
CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT? HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? THANK YOU
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MPD Files
Hello, I am trying to debug the sdram interface on a custom board I built. I need to look at some of the internal signals of the PLB_DDR interface. I modified the VHDL code and the .mpd file. However,...
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low cost xilinx prom burner?
I need a production station that can (a) burn my xilinx xf08p serial prom and (b) xdownload some code to be burned to flash. I currently have to use Impact for the prom and XMD for the flash. I don't...
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ACTEL ProAsic Plus
I have some very basic problems getting simple things to work on this platform. Is there a quirk of this product this i don't know about?? seem to have problems with counters and state machines..
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Need help with VHDL simulation with SPW in Linux
Hi every one. I am newbie in FPGAs, although I can write VHDL. I already setup a copy of Cadence SPW 4.82 from my company to study FPGA myself. My OS is Scientific Linux 3.08 (clone of Redhat...
 
System Requirement to run V4Lx200,v5lx330
Hi guys, Our comany trying to buy a new board with V4lx200 or v5lx330. to run MAP in ISE for these FPGAs. I would like to know any is working in such boards. And what type of system will be needed for...
 
Testing FPGA
Hi guys, I am working in the FPGA's for the last one year. I never doubted the working of the FPGA, but now i want to know whether there is any procedure or methods available to test the FPGA. I mean...
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best way to get 4xclk
Hi, What is the recommended way to get 4xClk from Clk? Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. Then is there any recommended way to get this? Regards, JK
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need help on our thesis proposal in our school.
We are currently proposing to do a FPGA based fm receiver using VHDL. We are newbies in the VHDL programming and we are currently reading books and journals about it. We are students in the...
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Nexys from Digilent... aka, binge hacking
Recently I ordered a Nexys Spartan3-1000 / Cypress FX2 USB board from Digilent for work. It's been fun and I may well buy one personally, but like aways there are the suprises, the silly mistakes, and...
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Xilinx ISE WebPack Simulation Problem
I am trying to perform a simple behavioral simulation of a baud rate clock generation module. The module is straightforward and will synthesize properly, so I am fairly confident that it is written...
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LUT based virtex multiplier
Hi, I wonder if someone could suggest an efficient LUT based signed multiplication algorithm for Virtex FPGAs. I've implemented an unsigned multiplier using the "computed partial product multipiler"...
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