Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Spartan MicroBlaze
Hello, Does anyone know if there is a Spartan based uBlaze development board that has SRAM on it? Best regards, Rob
4
4
 
[Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
Dear all, I am using Syplify8.5 and Xilinx Webpack 9.1 to implement a CPLD XC95144XL, Verilog simulation showed everything fine, but P&R showed a warning message as follows Cannot apply TIMESPEC TS_WR...
1
1
 
Altera PowerPlay Power estimation
Hi, I am trying to evaluate the power consumption of one of my design. But the powerplay power analyser keeps telling me that the metric confidency is low, because much of the toggle rates are...
1
1
 
ISE:Simulation
Hi, I have a process in my code that is decides if enable pin of a counter is high or low. When i start my simulation the process is triggered by one of the signals in the sensitivity list and the...
1
1
 
How can we know how many BRAM are used?
Hello~ I'm beginner and so looking for someone who know how to get the infomation about the number of used BRAM from reporting file. I think that it would be like "Dual Port Memory". is it right?...
1
1
 
Handel-C, multiple clock domains, and PAL library
Hi, Currently, I'm doing some experiments with multiple clock domains and Handel-C (by Celoxica). However, as far as I know, it is not possible to call PAL library in different clock domains. I do...
 
Xilinx and archive of Teaching Materials
Hi, I'm looking for archive of Teaching Materials (especially, Xilinx FPGA Design Flow Workshop Materials). Those available at are based on the Xilinx ISE v.8, but I'm interested in these based on...
 
Modelsim (errno = ENOSPC) error
Hey all. I dont know whats happened my Modelsim but anytime I try and do anything with it like open/close/create a project I get this error: # ** Error: (vsim-7) Failed to open ini file "tmpfile" in...
2
2
 
$recovery
Hi, I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I checked the timing report. Everything is ok, and there is no timing violations. But when I run post simulation, the modelsim...
4
4
 
spartan 3E USB port... use for i/o instead of programming
can it be done? where do I look for information? Rich
2
2
 
Verilog Programmer / FPGA Analyst
Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are seeking someone who knows the C programming language and has experience with Xilinx...
 
Redundancy
Hi all I am working on partial reconfiguration and I am stuck. Say I have an INIT value of "8000" and I am changing it to "8800" the third input seems to be redundant and is removed from the routing...
1
1
 
OFFSET and Data Clock Skew?
Hello, I'm trying to register some data coming from an ADC at 4ns period. I currently have the following in my UCF: NET "adc_clk_p" TNM_NET = "TG_adc_clk_p"; TIMESPEC "TS_adc_clk_p" = PERIOD...
1
1
 
Spartan-3AN
finally announced! so now can talk about them - well still not documents on Xilinx website, but hopefully they will be available shortly Antti
40
40
 
ML501 Platform Flash Configuration
Hello All, I have a Xilinx ML501 board and I want to use the Xilinx XCF32P platform flash to configure the XC5VLX50. I can program the LX50 directly accross the JTAG chain and the design runs...
2
2