Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Introducing picosecond delay between two output signals
Hi, I would like to know what are the common methods of introducing delays as low as 10ps between two outputs in an FPGA. I do not currently have a specific FPGA in mind. I am just looking for a...
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15
 
DFF with clock and async-preset tied together
Assume we have this VHDL model process(sig) begin if ( sig = '1' ) then q
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1
 
Spartan3AN - Roadmap
Hi, I just got a newsletter stating the Spartan3AN being available now. While these Spartan3AN are market as "new non-volatile" FPGAs, this might (IMHO) be misleading. For my understanding...
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22
 
DCI termination mismatch error reported in ise91
Hi : i am using ise 9.1i to run my designs which containted lvds . In my ucf file , there are constrains like NET "Ring_In_P[47]" IOSTANDARD = LVDS_25_DCI; but later on in phase of map of ise , it...
 
Query regarding Project.Plz help very urgent
Hi, I m doing a project on "IEEE 802.3 Packet generator on FPGA".The details of my project are as follows There are two swithes on the FPGA to input 4 different lengths of data between 0 to...
9
9
 
Where do I find CMOS image sensors and lenses?
Hi everyone, I would to interface a CMOS image sensor to my FPGA. I'm looking for low-end sensor and a matching lens. Nothing fancy or several mega pixels - just the bare minimum. Do any of you have a...
7
7
 
No Clock in ChipScope Pro Analyzer
I setup a CDC test configuration using ILA in Chipscope Pro ver 8.1.03i. There is activity on bus and on data lines in the Analyzer but the system clock (BUFGP) of which the core is running is dead in...
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4
 
Routing problem of DCM
Hello, all: When I did the implementation of my design, the map process gave me the following error:...
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8
 
ISE & EDK on 64 bits linux machines - install story ;)
Hi, I've just installed a brand new machine running Gentoo AMD64 with a 64 bits kernel and a 'multilib' userland. (That is, I have some emulation libraries for 32b apps). Here's my experience at...
 
Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
Hi guys I'm trying to synthesize processor core with ROM and RAM in the VirtexE FPGA. I've created RAM memory using VirtexE Block RAM resources by means of 'Single-Port Block Memory Core Generator' in...
5
5
 
Xilinx Ise 6.3i
Hello, does anybody know how can I get xilinx ise 6.3i? I have installed ise v8.1i, but know in my organization I need to install ise v6.3i. Thanks
1
1
 
A Very good VLSI Chip design website
Hi Designers, The website dedicated for we(VLSI Chip designer's discussing about trade-off's /problems solutions/ FAQ's)... I found a very good website for VLSI Chip design, which has columns for all...
2
2
 
VHDL and Latch
Hi, I am very confused with latch generation in VHDL. 1. I have been using VHDL for 7 years and I have never met a situation I need a latch. 2. I want to know why VHDL let VHDL programmers guess what...
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37
 
Multiple devices within one ISE project
Is it possible to use an ISE project to compile for multiple devices? I happen to have a project that can target two different boards with different FPGAs. Most of the files are the same, besides the...
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6
 
Xilinx: it's about time!