Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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direct access on opb_emc
I have a usb phy chip sitting on my opb_emc. I always have to use XIo_Out and XIo_In to access. Direct read/write to these addresses doesn't work. My problem is the access time is 100x slower than it...
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17 years ago
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QuickSilver's ACM architecture
I am seeking information on QuickSilver Technology's "Adaptive Computing System" framework. Their infrastructure sounded like it would be a really good fit for some work we are doing at NASA MSFC. It...
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17 years ago
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IOSTANDARD default value in Xilinx UCF-Files?
Hi there! I am wondering what the default IOSTANDARD is on pins for which it is not explicitly assigned in the UCF of the project. Here, the project uses LVCMOS25 for some pins where nothing is set...
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17 years ago
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Jam STAPL Player extensions
Hi All, I have sent to very "quick & dirty" extensions to Altera's Jam STAPL Player, allowing it to work with multiple JTAG chains interfaced with SCANSTA111 bridge, and making programming faster,...
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17 years ago
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ADC capture with FPGA Spartan3 in Verilg
Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampling frequency 8Hz, show the data capture in array leds....
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17 years ago
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FPGA vs. GPP anyone?
Hi, I couldn't find any comparison between FPGA and GPP. I thought I could get some of the expert two-cents on this matter especially in terms of cost, power and performance from this group. Cheers,...
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17 years ago
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CFP : FPL 2007 (Submission deadline extended to 25th of March)
******************************************************************************* 2007 International Conference on Field Programmable Logic and Applications Call for Papers...
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17 years ago
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how to transform Arun's LDPC code to max-product (Min-sum)?
how to transform Arun's LDPC code to max-product (Min-sum)? comp.dsp LDPC Advice would be appreciated on how to transform Arun's code given on sum-product to max-product (or min-sum) algorithm. He...
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17 years ago
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How to find pcore directory from within EDK TCL script?
I am working on TCL scripts that go with EDK pcores that I am developing. The MPD file allows me to specify that I want TCL functions in the files I provide to be called at certain times. I would like...
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17 years ago
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Eval board advice
Howdy, I'm looking at Xilinx FPGA boards in the $300 range. In a grad school course I worked with a Memec Virtex II-Pro board (V2P4 single PPC core) using EDK. I'd like to continue developing my...
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17 years ago
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XPower crashes....
Hi, I do a post place and route simulation using modelsim. To estimate the power I generate file during simulation so that I can get the power numbers using XPower. The problem is that XPower at the...
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17 years ago
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Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
Hi, In my many projects, some signals have both positive reference and negative reference, does it cause an additional LUT delay? For example, in the following statement Rx and not Rx are both used...
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17 years ago
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Xilinx XST 9.1, Verilog 2-D arrays, always @*
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* block. Here's a (perhaps poor) example: reg signed [15:0] table [0:255]; reg signed [23:0] sum; integer i; always @* begin sum...
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17 years ago
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Systemverilog preprocessor allow "..."?
ANSI-C preprocessor supports a 'wildcard' ... #include #define _NOISY_PRINTF( ... ) printf( ... ) #define _QUIET_PRINTF( ... ) int main( void ) { _NOISY_PRINTF( "hello world, %d, %d, %d! ", 1, 2,3 );...
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17 years ago
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What official function should I call to genertate a sum of products in VHDL
Hi, What official functions should I call to genertate a sum of products in VHDL? S(...)
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17 years ago
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