Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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1.8V config proms for Cyclone 2s
Hi folks, Is it possible to get EPROMs for Altera (Cyclone 2) devices that work at 1.8V? I appreciate the help and insights. Best, Sanjay
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17 years ago
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FF's are inffered instead of distributed RAM
i have a byte array of size 10 and i need to shift values in the array to left by 5 positions in 5 clocks. here is the code im using. reg [7:0] data[0:9]; // data shifting process reg ps_shift_start;...
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17 years ago
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Using xilkernel with C++
Hi, is there a way to get the Xilkernel to run with a C++ application? I didn't find any option for this in the XPS "Software Platform Settings". The problem I'm having is that my thread function...
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17 years ago
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FPGA with 5V and PLCC package
We use in a laboratory course still XILINX XC3000 FPGAs with Viewlogic's Workview design entry (DOS version) and XILINX XACT (also DOS). The problem is that we have to replace the old PC's and that...
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17 years ago
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Automatically adding pcore from XBD (Xilinx Board Definition) file?
Hello everybody! I am slowly making my way getting our custom Xilinx Virtex-4 based board to work. Today I got as far as running the Base System Builder (BSB) from the Embedded Development Kit,...
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17 years ago
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prog_b held low?
working with a custom board with a V4 on it. It has been working fine for a couple of months until last week - when the FPGA would just not come out of reset. I tried running a JTAG boundary scan...
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17 years ago
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timing in xilinx fpga
Hello everybody, I am using Xilinx Timing Analyzer in order to see average delay per each wire type, i.e. for double, hex, long and single in Virtex II chips. I found two nets where the number and the...
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17 years ago
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create test bench of video
hi every body , i m asked to read a video using an FPGA , can you please give me some ways that let me adopt to create the test bench of the video? it means what are the different ways to read video...
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17 years ago
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Wanted: container classes for reconfigurable computing
I did some search on the topic and the results were quite disappointing, though I would expect something like that should exist: I am working on a theoretical, combinational problem. My software...
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17 years ago
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Xilinx ISE Inferred block rams
I am getting a warning on 18 and 36 bit wide block rams inferred in my Verilog code in ISE 9.1. The following code is an example of what causes the warning. I do not get warnings on 16 or 32 bit wide...
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17 years ago
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Sparten 3E clock generator
What is the best way to generate a 125Khz square wave? The DCM only goes down to 5Mhz. Thanks.
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17 years ago
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ModelSim PE exit code 211
When I try to run a timing simulation (simprim is used) modelsim pe student exits with fatal error and exit code 211. Modelsim XE works fine, but sloooow. Does anybody has some experience with this...
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17 years ago
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Altera introduces Cyclone III devices, ships 65nm
Hello: Today, Altera announced the Cyclone III device family. Highlights: Industry's first 65nm low cost FPGA Shipping now (yes, really) Up to 120,000 logic elements, Up to 4 Mbits RAM, 288 18*18...
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17 years ago
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a project work
hi all i am an engineering final year student in english i am doing a project on "CONFIGURING FPGA USING XC9500 CPLD AND PARALLEL PROM" i am staring frm the scratch i studied some literature... but i...
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17 years ago
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alliance tooset on Linux
I'm trying to install the alliance toolset on an Ubuntu linux machine. I've downloaded both a tarball and RPM sources. The site says to see the README to install the tarball, but there is no README....
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17 years ago
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