Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??
Hi, I would like to load a on-chip ROM in a Altera Stratix device with the data produced by the linker script shown below. Since the text segment is not located at address 0x00000000, ModelSim, or...
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17 years ago
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convertion real to std_logic_vector
Hi , please my problem is how to use real constant for example 0.1913 and multiply it with an std_logic_vector(7 downto 0) and as an exmple to remplace reals b std_logic_vector , i did find that -- Y...
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17 years ago
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shift register with distributed ram
is it possible to implement a serial in , parellel out shift register from xilinx distributed ram? any guidance is appreciated.
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17 years ago
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Amphion IP MPEG2 Video DecoderCores
Has anybody ever used the Amphion CS6651 Cores targeted for either Xilinx or Altera FPGAs? I am currently using the Video core on an Altera Stratix FPGA and I am having trouble getting the core to...
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17 years ago
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iMPACT:CRC Error bit is NOT 0
Hi everybody, I am using XSA-3S1000 v1.0 and XStend v3.0. Tools are Xilinx ISE 8.1i and EDK 8.1i. I created a simple project in EDK. Then I downloaded If I used XSA-3S1000 board standalone, so iMPACT...
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17 years ago
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EDK and Custom Peripheral: error occur when generating bitstream
hi all, first, i am sorry for my poor English. i use EDK 7.1i and ISE 7.1i. imported custom peripheral with PLB Master Interface ( not from IFIP ) into my .xps project after overcame several problems....
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17 years ago
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Custom IP ports to be used as GPIOs
Hi, I have attached my custom IP to the OPB bus. The Custom IP contains ports which should directly interact with the outside world. I have ML403 board. I want to connect these ports to these GPIOs....
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17 years ago
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Flash memmory model
Hi all, In my new firm we are planning to develop a flash model. What i want to know is that is there any need for such an activity. My feeling is that all the vendors will provide a beautifull timing...
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17 years ago
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problem while using if or case statements
hai , i am vishnu, i am doing my project in verilog using state machine, while using if or case statements i am getting some error . i have coded like this s4 : begin if ( {gsr,gsy,gsb} == 000 ) begin...
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17 years ago
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IEEE 802.3 Ethernet MAC implemetation in FPGA
When I am sending some frame from the PC to MAC implemented in the ML-402 board, It receives the whole frame with proper data, but not able to calculate FCS properly and generate a error signal for...
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17 years ago
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URGENT HELP NEEDED: LVDS
Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus between the 2 FPGAs. -1 INPUT from an external board. -1OUTPUT to the same external...
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17 years ago
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multiple clock domain issues
Few doubts I would like to get clarified, 1. Weather synchronizers are required for control signals only or for data signals also? 2. Internal to FPGA, suppose 2 different clock domains are there - do...
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17 years ago
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Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Module ( and I am having all sorts of problems. One of the main problems right now...
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17 years ago
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Parallel Cable IV in Spartan 3E???
I am trying to configure Spartan 3e (Starter Kit) with a Parallel Cable IV (J28) with flying leads instead of USB. The reason is that I must use flying leads with other fpga and first of all I prefer...
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17 years ago
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Matrix inversion in FPGA
Hi all, I am working on a project which needs matrix inversion (dense matrix) of order 40x40 with floating point numbers. I am in need of help in doing the same with systolic array architecture in an...
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17 years ago
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