Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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EDK 9.1i installation
Is EDK9.1i a free upgrade if you have EDK8.1 installed and does anyone know where it can be found. Sven
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17 years ago
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Dear Xilinx
Dear Xilinx, I updated my WebPack Saturday night. Thank you for making these available. I have been unable to get my Spartan 3E Starter Board to work with the DDR SDRAM since I got it four months ago....
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17 years ago
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how to use and calculate prom checksum in prm file.
this is part of the prm file PROMGEN: Xilinx Prom Generator J.30 Calculating PROM checksum with fill value ff Format Mcs86 (32-bit) Size 512K PROM start 0000:0000 PROM end 0007:ffff PROM checksum...
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17 years ago
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broken mb-gcc -O2 ?
Hi, I'm compiling this code for microblaze gcc void uart1_printchar(unsigned char c) { while( (*(unsigned char *) UARTS_STATUS_REGISTER) & UART1_TX_BUFFER_FULL ); *(char *) UART1_TXRX_DATA = c; } and...
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17 years ago
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DCM_STANDBY macro in Virtex-4
I was obliged to go back to Virtex-4 Stepping Level 1. So I'm now faced with the DCM problems. Should I use the DCM_STANDBY macro for each DCM on the FPGA or only for the instantiated ones? Thanks in...
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17 years ago
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Question about initializing the ram value in test bench
How do i initialize the ram value in test bench? And how do i read back the value. The following codes is what i have tried but i read back the signal as undefined ("UUUUUUUU"). Can someone help me...
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17 years ago
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How much time margin should I give to a SDRAM interface via FPGA?
My altera FPGA is connected to a SDRAM on the prototype board. Assume the clock frequency is 100MHz, how much margin should I give to the SDRAM? 3ns? 5ns?
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17 years ago
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Spartan-3A XC3S1400A development board?
Greetings, Would anyone happen to know where if could purchase an FPGA development board with the Xilinx Spartan-3A XC3S1400A FPGA on it (or a socketed board capable of accepting an XC3S1400A) please?...
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17 years ago
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Altera ASMI_PARALLEL megafunction (EPCS4/CycloneII)
I'm using a EPCS4 to configure my CycloneII in AS mode. ALTASMI_PARALLEL megafunction. Doesn't seem to work. With the scope I can see my clock on the DCLK pin, but there is something iffy about the...
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17 years ago
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microblaze bootloader
Hi, I am using XPS to program my application onto the Xilinx Virtex2 pro board. The size of the application is upto 1 MB and hence I need to reference instructions from the external DDR memory (2GB)....
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17 years ago
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ISE on Fedora?
I am running Fedora 6, and I am having trouble installing ISE WebPack. When I run the setup program it tells me that I don't have the right version of libstdc++, so I installed the compat-libstdc++...
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17 years ago
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Config PROM for Spartan II
Hi all, at the moment, we are using AT17LV010 configuration devices for a spartan 2S100. I have to look for a different solution which is not so expensive. The Xilinx XC17V01 is OTP and more expensive...
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17 years ago
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Static RAM implementation with VHDL
Hi Dear all, I need an implementation of a STATIC RAM with VHDL; I need this RAM to work with/without read buffer and with/without partitioning. Could you please help me? Thank you in advance.
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17 years ago
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Help with a face recognition system
Hi all, I am a Computer Science student in my final year. My graduation project is to build a face recognition system (based on Principle Component Analysis and possibly Artificial Neural Networks) on...
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17 years ago
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Sysgen compilation target
Hello, I am trying to create a new compilation target for SysGen and I found that the documentation is not complete and the sample compilation target that is provided with SysGen is not working. Did...
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17 years ago
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