Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Problem with PHY clocks on Spartan 3E Starter Kit
Hi, I am designing a ethernet block using the Spartan 3E Starter Kit. The design will be using the RX and TX clock provided by the SMSC PHY on FPGA pins T7 and V3 on the Spartan 3E Starter Kit. I have...
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Conceptos about VCCINT,VCCAUX,etc
Hi!, Maybe this doubt is stupid but nobody has explained it to me so could you help me? What are the functionality of the listed elements into the FPGA? Why are there several of them into the FPGA?:...
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MIG under Linux
Hi everybody, Did someone tried to install MIG under Linux using Wine? Cheers Mehdi
 
Looking for Memory Recommendation for Spartan 3E 1200
Hi everyone, I'm working on a Board for Bus Interfacing and some Audio Processing, which will use Spartan 3E 1200 and the Microblaze. Now I'm not sure what kind of memory I should use. Size ist not...
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Boot PowerPC on VirtexIIPro
Well I have a strange problem. I have a VirtexIIPro30 on a Sundance target. I use XPS 8.2.02 to create a design with a 16KB of plb_bram_if_cntlr, and GPIO LED with bandwith 2. I add a Test_App...
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RFC: VHDL testbench enhancements
Hi, Let me try this again. The VHDL standards community has been considering whether to enhance VHDL to add advanced testbench features. If you are a VHDL user, Do you want these features added to...
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QUIP write_verilog.c
Hi- I have been using the QUIP package and have one question regarding integration with SIS. I have been reading the quip_synthesis_interface.pdf document included with the QUIP documents, and am...
 
re-assemble bootloader for NIOS Processor
Hello, I want to recompile the bootloader for the Nios processor. The reason that I want to do this is: - I use an EPCS flash - by default Nios code is situated directly after the FPGA bitstream - I...
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Implement IIR Filter on FPGA
hi people, I'm designing filter system called IIR filter on the FPGA kit, but it doesn't work when I implement on FPGA. When i iput the signals, the output results seem to not get any thing. I do not...
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ISE 9.1i SP3 simulator problems on Linux
When trying to run the WebPack ISE 9.1i SP3 simulator on Linux (Gentoo, specifically), it always stops building the simulation executable with a message such as: Building counter_tbw_isim_beh.exe...
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X_OBUF and other error messages with ModelSim
I am trying to perform a Post-Translate simulation of a design, but I'm getting a huge number of errorts that are basically a replication of these following 3 erros: # ** Error:...
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Does the XC3S250E-VQ100 exist?
I have an application that is very space limited, and would like to use a Spartan XC3S250E in the VQ100 package. Even this package has more I/O than I need. (I need a lot of logic, but communication...
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Dynamic Reconfig
Hello, I would really appreciate if you could give me some insight on the following -Can you guide me to a link/example which runs thru the process of dynamic reconfiguration on Virtex2/4 step by...
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MGT Digital Receiver Oversampling
I started working with the MGT's recently on a V4 PCI-E development board. I am just using the digital recevier in oversampling mode. Everything is working as expected. I put serial data in and get...
 
Standard PCI Xilinx board with Ethernet port
Hi All, Would anyone please tell me to find a standard PCI FPGA Xilinx board with ethernet port ? Thanks Thuy
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