Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Looking for Xilinx fpga board that works in Linux and has Ethernet card
I am looking for a FPGA board which supports some features: 1- PCI interface 2- 1G ethernet port 3- Linux driver support 4- Less than 1,000 USD Would any one please show me the suitabe cards or give...
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17 years ago
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ByteBlaster Parallel Driver for Linux > 2.6.13
Evnin' As Linux versions after 2.6.13 don't have devfs anymore... will there be soon a new version of the byteblaster.tar.gz parallel driver or has someone a patch for it? cheers rick
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17 years ago
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Measuring the period of a signal
Hi, I am trying to measure an input signal that will be a square wave of a certain unknown frequency in the range 1MHz to 4 MHz using an FPGA. I have no control over that input signal. The FPGA should...
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17 years ago
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Clocking data into a shift register on positive AND negative edges
Hi, I'm trying to design a floppy disc 'raw reader' (to archive discs that have been written in unusual formats that PCs can't read). I've got a basically working data separator design that turns the...
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17 years ago
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How do I use the Xilinx USB download cable for testing?
Fellow Designers, I am looking for a more convenient way to use inexpensive eval boards to test logic designs in an fpga. I do this quite a bit already by designing stimulator logic to put in front of...
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17 years ago
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query
I am implementing IIR Filter in verilog with equation y(n)=a*x(n)+(1-a)*y(n-1) a is floating point no with 5 bits x is integer with 7 bit input .y(n) is 12 bit with 5bits floating and 7 bit integer...
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17 years ago
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Xilinx ISE constanly asking to regenerate a core file.
Hi everyone, I have a very simple ADC controller in VHDL, plus a Xilinx FFT core. There are only 2 files in my project: ADC_control.vhd and myfft.xco Every time I try to create a new bit file, ISE...
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17 years ago
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raggedstone + xc3sprog?
Hello, all... Has anybody gotten xc3sprog to work with the raggedstone board and its included parallel programming cable? I had to add an entry to devlist.txt for the configuration PROM (xc3sprog gets...
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17 years ago
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A new way to define systems of systems?
I have recently been playing around with what I think is a new approach to defining and implementing distributed embedded systems. I've come up with a language that I call SMIL that defines the data...
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17 years ago
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ispLever FTP Download
Hello... Why is it that the Windows Version of ispLever 6.1 is downloadable via FTP but not the Linux version? thx in advance rick
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17 years ago
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can anyone give me a reference price of the following Xilinx boards?
I can't check any price infomation about the following boards in xilinx website: 1) ML521/3/5 ---- Virtex-5 GTP characterization board. 2) ML550 ---- Virtex-5 networking development board. Btw: what...
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17 years ago
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How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
Hello, I am trying to implement an 8 bit adder program using VHDL on Virtex 2 pro with expansion kit DIO4 from digilent. The code is correct and I can see the result on 4 LEDs of Virtex 2 pro kit from...
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17 years ago
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XUP virtex-II pro
Hello I developed a hardware component in ISE which interfaces with my own- made print-circuit by using the lower middle expansion header (just for information). Now I want to couple this hardware...
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17 years ago
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Icarus Verilog
I just wanted to get a heads up from anyone out there about this tool. My initial results (for some trivial designs) were pretty good with the synthesizer Has anyone used this for any large synthesis...
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17 years ago
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Nios2: elf2hex settings for epcs bootloader
Hello, I have recompiled the assembler code for the bootloader of the Nios2. After this compilation I have an .elf file. Now I have to convert this elf file to a hex file which can be used as memory...
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17 years ago
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