Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
Evnin' Just received the ispLever Linux DVD today... Install went fine...but when setting up environment or trying to start: me@home ~ $ Creating local directory ~/.isplever_lin/ sed: error while...
1
|
17 years ago
|
1 | |
|
|
lwIP, temac, and DMA
The documentation for the lwIP core (v2.00a) shows that there's only support for FIFO data transfers when using the TEMAC core. Will there be support in the future for DMA/SG? I'm still using EDK 8.2...
—
|
17 years ago
|
— | |
|
|
POC at Element CXI
Does anyone know of a good point of contact at Element CXI? I am currently doing an evaluation of potential platforms / architectures for an upcoming reconfigurable computing application development...
2
|
17 years ago
|
2 | |
|
|
has anyone used mathstar field programmable object arrays?
Just wondered if anyone here has used these devices... I want to do embedded computer vision applications and it sounds like they are a pretty good fit. But I have no idea about the difficulty of...
3
|
17 years ago
|
3 | |
|
|
Wanted: XUP Virtex II Pro DDR-controller
Hello I need to create a dual port ram from my DDR-RAM from within hardware. But I can't figure out how to make it work. So my question, is there anybody here who already made something like that and...
—
|
17 years ago
|
— | |
|
|
Help!! FIR Polyphase second - order interpolator
i need a efficent FIR Polyphase second - order interpolator code i want to use it on Cyclone II .Plese help me ,Thank you!!!!!
1
|
17 years ago
|
1 | |
|
|
FIFO newbie question
Hi all, I'm designing a small project which uses the primitive FIFO_16 of virtex 4. The problem is: This FIFO uses an asynchronous reset, which resets all flags and internal registers of FIFO. Reset...
4
|
17 years ago
|
4 | |
|
|
Query in Parallel CRC(urgent)
Hi, Can anyone plz tell me the theory behind 32bit parallel CRC? i m not getting the basis on which the 32 bit CRC is being calculated in the code code is generated from the CRC tool of wesite refered...
2
|
17 years ago
|
2 | |
|
|
Please HELP: timing problems on Virtex-4FX
Hello, I am working with the ML410 board and the V4FX60 FPGA. For the past week and a half, I've been having problems meeting timing and I just can't figure out why. In my design, I need to use DDR2...
5
|
17 years ago
|
5 | |
|
|
Xilinx WebCase support
I have a webcase open since 3/20. Though I have been given decent support I find that I get one and only one email from Xilinx per day...at most. Even if it is a simple response, there is no...
7
|
17 years ago
|
7 | |
|
|
CPLD + µC with reasonably-priced tools?
Hi all, I have a potential (hobby) project, where I'm looking at needing, in effect, a CPLD and a µC that can share memory. +5 V I/O tolerance is necessary (for about 52 signals coming into the...
12
|
17 years ago
|
12 | |
|
|
Flip Flop problem (asynchronous or synchronous???? )
Hi everybody, i have a missunderstanding of the flip flop behavior: usually the output of a flip flop is assigned its input of the previous clock period (that's true for internal signal), but i...
9
|
17 years ago
|
9 | |
|
|
Problème de bascues (asynchrone ou synchrone?)
Salut, il y a un ph=E9nom=E8ne =E9trange que je n'arrive pas =E0 comprendre: normalement lorsqu'on consoit une bascule synchrone sa sortie correspond =E0 la valeur de son entr=E9e durant le coup...
2
|
17 years ago
|
2 | |
|
|
EDK 8.2 MicroBlaze Tutorial
I am trying to work through the "EDK 8.2 MicorBlaxe Tutorial in Spartin 3" When I get to the point of "Generate Programming File" to implement the design on page 26, It appears that ISE does not call...
—
|
17 years ago
|
— | |
|
|
Available: Detailed RISC CPU IP Core Design Documentation
Hello, I have put up an article on our web site that describes a RISC CPU IP Core that was created for one of our clients: The RISC IP Core is instruction-compatible with the Microchip...
—
|
17 years ago
|
— |