Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Issues with the BBD file, using a core generated using ISE coregenerator
Hi all, I have a few issues with how to use the BBD file. key words ISE 8.2, XPS 8.2, BBD file, CORE Generator step1. I create a core using coregenerator, generate .ngc (netlist) file out of it....
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17 years ago
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There is something (other) like his?
Jamma platform for gaming with SDK Thanx
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17 years ago
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Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals. We need to connect a CMOS image sensor and a FPGA chip. The distance between them is...
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17 years ago
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Compiling a library
Hello, I am trying to simulate a VHDL code (using ISE 9) and I am getting the following error: ERROR:Simulator:235 - Package XXX_pkg has not been compiled properly. Please recompile package XXX_pkg....
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17 years ago
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Printing problem with Ise 9.1.03i
Hi all, I'm using Ise 9.1.03i. when I try to print a code written in Ise text editor, I get this error: "Print fails because the default printer has not been selected", and when the design summary is...
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17 years ago
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ISE Smart Ident
Hello, Is there any facility in ISE to automatically indent source code? The similar technique is available in C/C++ editors and I it is very simple to add it to ISE for indenting smartly VHDL and...
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17 years ago
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BFM simulation and number of Masters?
Hello, First of all I will make my question: Could you please say me how many Masters can be connected to the Bus when the BFM simulation is been used? I created a coprocessor for the embedded...
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17 years ago
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Analog FPGAs: how fast?
What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel Fusion.) For example, if I wanted a gated integrator with a sub-microsecond...
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17 years ago
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ModelSim Waveform naming question
I am using ModelSim SE and was wondering if there is a way to make a waveform display mnemonics. I am simulating a state machine and it would be convenient to have the waveform display the state name...
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17 years ago
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Any recommendations for FPGA PCI development board?
I want to buy a FPGA PCI development board supporting the following features: 1. Large FPGA device, Xilinx FPGA prefered, especially Virtex2p/ Virtex4/Virtex5 series. 2. PCI(33M/32bit,66M/64bit)...
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17 years ago
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Block RAM strange behavior, address off by one
I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every time I issue a read, the word at the location previous to the given address is read. For example if I'm reading from address 5,...
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17 years ago
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creating library in ISE 9
Hello, I am newbie in VHDL. I want to create a library with several pkg on it so when I am creating a new library; I could add it to my new project and then use the pakage. What I am doing now is as...
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17 years ago
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80000 Bit Shift Register
I am implementing an 80000 Element Shift register to be used as a very long (1Sec) digital delay generator. (Yes, its that big). It is clocked at 80kHz. Its a very simple design, just an ordinary...
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17 years ago
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No Synplify evaluation?
Good afternoon.. Has anyone being lucky in the past getting a Synplify for Linux evaluation license? Mentor has some online feedback form to request an evaluation license, but apparently their eimail...
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17 years ago
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xilinx unused I/O state
Hi, What is the default state of the unused I/O pins for Xilinx FPGA (Spartan 3E)? For Altera FPGA, it can be set as input tri-stated or as output driving gnd, etc. Is there any counterpart operation...
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17 years ago
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