Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
I am trying to analyze amount of the FPGA (V4) resources used by each of my hierarchical blocks. I am not sure if there is a better way, but I am trying to use the information available in the...
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17 years ago
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Raggedstone1 LVDS Oscillator
For those of you that have been waiting for this module the LVDS oscillator module for our low cost Spartan-3 Raggedstone1 development board is now available. Details here is capable of generating...
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17 years ago
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simulating with OSe 9.1.3
Hello, I am new in FPGA. I am using ISE 9.1.3 on windows. I wrote some VHDL codes and when I run the simulation ( from process window) the result that I am getting is correct but when I restart...
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17 years ago
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Memory generator IP core ISE Webpack
Greetings... I have been trying to use a block memory component (in this case just a single port ROM to start with... will be adding a dual port RAM once I get this part working) in ISE Webpack 9.1i,...
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17 years ago
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Ouputs during startup and Programming
Hi, I have designed a motor controller with the Virtex 4 FX-12 Mini-Module and I of course would like the PWM output pins to never go high during startup or programming. They do go high during this...
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17 years ago
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Question about intalling EDK9.1i
Hello, I intalled the ISE9.1i and updated it. It can work. Then I installed EDK9.1i. But when I run it, it told me "The procedure entry point ptw32_push_cleanup" could not be located in the dynamic...
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17 years ago
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Looking for a spartan 3 board
I'm looking for a (low-cost) spartan 3 based board, containing a low to medium sized spartan 3 fpga, two 100 MSPS 12 bit AD converters, and ideally also one or two 8-12 bit DA converters, but I didn't...
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17 years ago
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FPGA Newbie
Hey Guys/Gals, I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was on a digilent board and the whole environment was set up for me. I'm doing my final year thesis for...
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17 years ago
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FPGA MAC for Point to Point Connection
Hi everyone, I've been reading previous posts regarding ethernet MAC layers for FPGA's but can't seem to solve my problem. I'm going to be sending a receiving UDP packets from my PC to a PHY chip and...
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17 years ago
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Stratix II - Cyclone II GATE COUNT
Hi, Is there an Altera application to count the number of equivalent gates for Logic Elements, Memory, DSP blocks, PLL etc... ? Thanks... I don't find this information..
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17 years ago
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FPGA Full Custum Design
Hi all, I am developing my first FPGA LUT-Based to make a FPGA with MRAM based design. There is anyone here who is an expert to the FPGA full custum design?
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17 years ago
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Virtex-4 module based partial reconfiguration problem
Hi I am experimenting on module-based partial reconfiguration for Virtex-4 (LX25-ff668). Intended functionality is that After full bitstream download on the board, LED blinks. After partial bitstream...
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17 years ago
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Clock signal FPGA XC95288xl144
Hi All, I have problem with clock signal in FGPA XC95288XL144. I have 3,3V signal on the output but I want get 5V signal. I say in addition that I use chip with 3.3V power supply. Should I use pull up...
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17 years ago
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DARNAW! - PGA Style FPGA Module
Finally first picture of Darnaw1 our PGA style FPGA board is here here More information on pricing and spec in the next couple of days will appear on the website. Those with eagle eyes can work it out...
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17 years ago
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questions about pci conmmunications on a pcb board
Hi, A PCB has been designed to faciliate communications between Virtex4 FPGA and an infiniband(ib) chip. The v4 fpga have a powerpc and the ib chip contains a pcix module. Now i have to design a pcix...
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17 years ago
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