Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
It seems there is problem with OPB in MPMC2 core. PPC will dead when 2 PPC share OPB peripherals in MPMC2 core
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16 years ago
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FPGA and DAC for wave generation
hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave, ramp, triangular and square wave generator which outputs...
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16 years ago
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How to add customer peripheral with IP core to EDK?
Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripheral uses a FFT core generated from Core Generator so it only comes with ngc...
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16 years ago
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I make a usb blaster for altera by myself!
it is work good!
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16 years ago
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Take verilog code from Xilinx Core generator
Hi everyone! I use Xilinx Core generator to generate DA FIR filter. Right now, I want to take the verilog code for DA FIR filter but I don't know how can I do it. Can you help me?
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16 years ago
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XTREME DSP Development Kit2 JTAG Problem
Hi all, I m using the Xtreme DSP Development Kit 2 with Viretex 2 XC2V3000-4FG676 FPGA. While doing JTAG cosimulation in Simulink, i got an error message:"Error configuring device: A problem may exist...
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16 years ago
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Slave PLB core interrupt
Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instantiated a OPB interrupt controller to which I'm trying to register my ADC driver...
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16 years ago
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I/O-Standards: HSTL vs. SSTL and others...
Hello all, my question - I/O-Standards - I have searched the WWW up and down, but I'm really not happy what I have found. Especially HSTL vs. SSTL - what is better, newer... Some...
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16 years ago
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free architecture
This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. Some nonfree architectures exist at the moment but it is known as a...
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16 years ago
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V5 GTP question
I have an application where I need to use 20 V5 GTPs each running at 3.2 Gbps to trasmit data out to a source synchronous device. I will have a separate FPGA for 20 channel transmitter and separate...
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16 years ago
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Problem with real data type
I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a problem with the signals defined with the real data navigator indicates that the...
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16 years ago
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Non-intrusive readback on FPGA configuration data
Hello, I was wondering if anyone knows if it's possible to perform a "non- intrusive" readback operation on the FPGA configuration data in order to verify its correctness and to ensure that it hasn't...
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16 years ago
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DONE problems
Hi, I am having a problem with a design. When DONE cycle is set to 5 or 6 DONE pin never goes high. I have confirmed that the part is configuring by scoping the output from the DCM. The part is a...
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16 years ago
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VHDL editing with UltraEdit
Hello, I decided to test UltraEdit to see how good is it in reformatting a VHDL code and indenting smartly. To do this I installed ultraedit and I did a test by asking UE to reformat this code for me:...
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16 years ago
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Lattice pricing
Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the approx. prices for their new ECP2 devices in quantities up to 100? Strange that...
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16 years ago
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