Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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OPB master and slave interface for DDR SDRAM controller
Hi, I am almost new in google gruops. I build IPIF master to control OPB DDR SDRAM controller. Using Create/Import Peripheral, I could make a IPIF master. In the folder of IPIF master, there was a...
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16 years ago
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Using OPB PCI In EDK 8.1
(This is my third attempt to send the same post to the group. The previous two posts still have not appeared on the group.) Hi I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have...
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16 years ago
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physical chip size
Dear I am looking at data book of Xilinx Virtex-II Pro to find ACTUAL CHIP SIZE. So far, I could not find yet -: (as an example, 900 um X 1.5 cm) I need a DIE (that we see in FPGA editor) size for...
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16 years ago
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Virtex-5 FX when ? (II)
Hello Antti, Peter and ..., yep, some months later now - the same question... V5-FX? Thanks and greetings Udo
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16 years ago
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Image compression on FPGA
Hello, i'd like to have some informations about image compression on FPGA hardware. Do you have some experiences with the Matrox Solios and in special the version with the Altera FPGA? I need some...
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16 years ago
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Using OPB PCI Bridge in EDK 8.2i
Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I am using a custom board with Virtex II, I include the PCI bridge during the BSB...
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16 years ago
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Using PCI in EDK 8.21
Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I am using a custom board with Virtex II, I include the PCI bridge during the BSB...
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16 years ago
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Incorrect response from MAC FIR Low Pass Filter
Hi all, thanks to your help, I have managed to solve the JTAG problem on my XTREME DSP Development Kit. However I had a response which attenuates all frequencies even though my design is low pass...
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16 years ago
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compact flash slave ip core
Where can I find the compact flash slave ip core for free,thanks!
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16 years ago
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XPS and inout ports: is it possible?
Hi, Im woerking on a Xilinx Virtex-II pro with Xilinx Platform Studio 7.1 My design has a bidirectional 8-bits bus. If I synthesize with Project Navigator and then I download the result using impact....
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16 years ago
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Problem with PowerPC PIT interrupt
I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP board. I need an interrupt to trigger so I run my scheduler at regular intervals, so I setup the PIT to trigger an interrupt at 1s...
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16 years ago
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The simulation library compilation wizard of EDK can't find modelsim
Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "modlesim is not found! please ensure that the simulator is correctly installed...
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16 years ago
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EDK Simulation library compilation wizard can't find modelsim
Hello, I am using the Simulation library compilation wizard in EDK9.1.01i and was told that "Modlelsim isn't found! please ensure this simulator is correctly intalled and/or the correspoind enviroment...
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16 years ago
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Altera DPA compatible with Xilinx IOSERDES?
Has anyone had success interfacing Altera DPA with Xilinx ISERDES/OSERDES/IDELAY? Is 1 Gb/s/pin feasible for Virtex-5 and Stratix-II? (did having both Altera and Xilinx on the same board cause some...
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16 years ago
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Increase memory resource at Xil_malloc.
Hi, I have to write a program with threads and when I reserve memory for these threads, an error occurs if this memory is big. I have configure Linker Script to run in Sdram so I have quite a lot...
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16 years ago
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