Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Problem with Lattice Diamond IPExpress software.
Not sure what to make of this problem, I am having IPexpress in Lattice Diamond generate a corrupted file if I define a RAM module for use with a soft CPU. I have a copy of the original generated...
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7 years ago
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Lattice Diamond and VHDL-2008
I don't have any trouble getting the simulation (Active HDL) or synthesis (Synplify) tools to work with VHDL-2008, but the Lattice tool itself doesn't seem to understand it. When Diamond analyzes the...
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7 years ago
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Active HDL Generic Controls
I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within the simulator. I see in the Design, Settings dialog box they have a Simulation,...
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7 years ago
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comparing hardware architecture
Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite sure which one to use Do you guys have any suggestions for FFT and DCT regarding...
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7 years ago
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Give God your all (live true faith)
Give God your all (live true faith): As the world dives deeper and deeper into self-absorption, seek your path from the strength and security of the living God. Learn of Him and His ways, and why they...
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7 years ago
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Advice to a newbie
I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I wanted to give it a go using FPGAs to design simple CPUs. I would like some advice on...
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7 years ago
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Article - Extinction Level Event
The synopsis of the guy's argument is: Given Intel bought Altera, and rumors that *comm is eyeing Xilinx, that's likely to shift the focus of both tier 1 FPGA companies to datacenters and away from...
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7 years ago
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Explicitly setting a variable to undefined
Hello, my question is probably best explained on a piece of code (the snippet is V erilog, but the question should be mostly language-agnostic) reg memory_access; reg[1:0] memory_access_size; always @...
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7 years ago
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VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free - and open source
UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectures....
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7 years ago
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Where do you want to go for eternity?
I saw this video today on the ComputerHistory channel on YouTube. The man cited, David Cutler, has been a pioneer in several low-level aspects of computer development while at Microsoft, and before: I...
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7 years ago
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A flawless execution
At the cross, Jesus took our filthy shame, and exchanged it for His spotless righteousness. No penalty. No condemnation. A full pardon despite our guilt. He makes all who receive Him perfect by His...
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7 years ago
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Multi-port memory
In this article on the second page there's a description of the memory architecture. A can't wrap around my head how did they configure 8 BRAMs to a 32KB memory with 12 independent ports. Can anybody...
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7 years ago
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Recoding openCV C++ project in pure verilog
I have a 6 month project to work with by hand-recoding openCV C++ project into pure RTL for FPGA usage. I have a Xilinx Zynq FPGA and I have Vivado. The code I am using are at , , and Anyone can...
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7 years ago
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Constraining data to out-of-phase clocks
I've got a project coming up in which one of the things I'm going to need to do is take in the 1 PPS output from a GPS receiver and align it to the 100 MHz frequency reference clock. The problem here...
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7 years ago
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Problem if compilation order in OOC compilations in Xilinx Vivado
Hi, Has anybody in this group faced the problem of incorrect compilation order of blocks selected for Out-of-context (OOC) compilation? It works correctly in case of blocks converted into packaged...
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7 years ago
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