Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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License problems with Quartus 7.0 on Linux
I've been trying to use Quartus 7 on Linux (I've tried three different RedHat/Clone distros, FC6, CentOS 5, Scientific Linux 4.4. The fitter is getting a license failure, Current license file does not...
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16 years ago
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computing branch metric for viterbi decoder
Hi, Hi, i saw the circuit for computation of branch metric in the following paper ( figure 3 a ), but i cant understand how it functions, can any body plz explain it. thanks. sawaak
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16 years ago
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Ubuntu and Webpack?
Has anyone tried to install xilinx webpack on ubuntu 6.06LTS? If I run the web download tool (sudo ./setup) I get through the questions but it dies shortly after I click install. If I use the single...
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16 years ago
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V5 GTP Transceivers supporting LVPECL
I have the V5 GTP transceiver differential output going to a non-xilinx receiver. The non-Xilinx receiver has following specifciation for its LVPECL input. Input High Common Mode range is 1.2V to 3.3V...
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16 years ago
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Help with ATF750CL and WinCUPL
I'm trying to code an 'enhanced' binary-to-7segments display decoder with ATF750CL and WinCUPL. I'm experiencing problems using the truth table CUPL construct , so I wrote these test code lines: Name...
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16 years ago
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FF setup and hold time.
Hi, can any one please clarify me that all the FF in the FPGA has same setup time and hold time values? If not why and where these different FF can be used? Thanks in advance. regards, Himassk.
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16 years ago
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UCF file for LT FastDAACS board?
Does oneone have a Xilinx UCF file for the Spartan Device on the linear technology FastDAACS board, and is willing to share it? Thanks, Thomas
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16 years ago
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VHDL core for Hitachi H8S or H8/300H CPU?
Hi are there anybody who have knowledge about some free VHDL core for Hitachi H8S or H8/300H CPU? Regards /Michael Wilspang
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16 years ago
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About DDR SDRAM
Hi everyone! I'm working with DDR SDRAM but I don't know how to choose row address and column address. Can you help me, please?
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16 years ago
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Disable Readback (XILINX)?
If i have an external SPI FLASH connected to the FPGA and uses 'Disable Readback' in the configuration. What does it do exactly? It is still possible to read the SPI FLASH externall?
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16 years ago
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V5 LVPECL Inputs
I have a differential driver with Vcm = 3.025V and Differential voltage of 1100mv. Thus each arm of the differential signal has 550 mV swing and Vcm being Vcc - 0.275V (3.3 - 0.275 = 3.025V). Looking...
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16 years ago
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EDK OPB_SPI in slave mode
Hi having trouble :(, all Xilinx and example only explain the used of OPB_SPI as master, as slave it doesnt want to work, any tricks or special care required? Antti
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16 years ago
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ANNC: Power Saving Design Techniques Webcast
Lattice is holding a webcast on Tuesday, May 15, "Power Saving Design Techniques with Low Cost FPGAs." The presenter will be Troy Scott, from our software marketing group. Please attend or pass along...
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16 years ago
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ISE Simulator :Does nothing when double click
Using ISE 8.2i I have created a top-level schematic and inside of it, wired some VHDL modules (as black boxes). I made my testbench and "added" it to the project. WHen i try to run ISE simulator...
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16 years ago
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Have you used an Altera altufm_i2c canned megafunction successfully?
I'm using the Quartus 2 canned i2c flash memory megafunction in a Max2 (EPM24T100C5). This is connected to a well-characterized i2c bus and is supposed to replace a 24c01 (known to work). It doesn't...
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16 years ago
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