Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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'EVENT (or rising_edge) static prefix requirement....
Can't figure it out... Why cant this compile: S_chan0_clk : process (reset_delayed, ch_clk_div_int) begin for k in 0 to 15 loop test_case := ch_clk_div_int(k); if reset_delayed = '1' then...
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16 years ago
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XILINX ISE 9.1i: DELAYCHAIN by input data
Hi, I am working on an DSP, have problem by data receiving. As listed below, xilinx ise tools build a "DELAYCHAIN" into the circuit, as a result, the data needs 7.956ns from PADS to FlipFlops. My...
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16 years ago
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About memory interface generater 007 tool
Hi everyone! When I use memory interface generater tool, I select device XC3S400. The tool dosen't generate verilog code for me. I don't know why. Can you help me to solve it, please?
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16 years ago
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ISE : Linux - coregen, compxlib errors
Hi I have installed ISE 8.2i on a AMD64 Linux machine running Ubuntu 7.04. ISE works fine, and Ican generate cores, HDL simulation libraries, etc from within ISE. But, my problem is the tools do not...
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16 years ago
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SelectMap or serial: How does the PROM know?
Hello, I am in the midst of reviewing a board design, which is based upon a (Xilinx) Virtex-4 XC4VSX35 which will configure itself as a master from a (Xilinx) XCF32P flash. The related schematics was...
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16 years ago
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ML405 LCD
How can I display "hello world" onto the Char LCD which is on the development board (ML405)? I realized a similar topic has been posted. But our situation is a little different. I want to do it the...
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16 years ago
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Xilinx VHDL Attribute syntax error
Hello, I was switching UCF lines to VHDL attributes when I came into this syntax error. Can someone suggest what the problem is? #UCF file works fine INST cam2_x0_ibufd_inst DIFF_TERM = TRUE; INST...
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16 years ago
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Chipscope with custom cable?
Hi. I'm debugging an issue with my board. The issue surfaces when several components interact, and I'm not able to reproduce the problem in a pure simulation environment. I heard that Chipscope is a...
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16 years ago
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An Open-Source suggestion for Xilinx
An Open-Source suggestion for Xilinx In generic the decision about to use Open-Source strategies is very complex, but there is an easy and low risc way to at least make the first step, the portion...
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16 years ago
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ISE 8.1
Hi there, I'm approaching ISE 8.1i. Trying to Simulate Behaviour Model I get the error message: "HDLParsers:164 - C:/Xilinx_Projects/tri_state_test/tri_state_tbw.vhw" Line 43. parse error, unexpected...
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16 years ago
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Altera FIR Compiler with clock enable
Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal? Have a look at my post at : I am trying to get a programmable coefficient filter to work with a...
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16 years ago
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How to add an IP Core to a Quartus project
I am totally new to all this, so please forgive my naive questions. I have a quartus project that runs on a development kit. All the pins are assigned and it works correctly. I wish to add an...
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16 years ago
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Second Call for papers - ParaFPGA-2007: Parallel Computing with FPGA's
======================================================== CALL FOR PAPERS ParaFPGA-2007 Parallel Computing with FPGA's A mini-symposium held in conjunction with the ParCo2007 conference "Parallel...
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16 years ago
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DMA with ipif / user_logic
Hi! For a small project running Linux on a Virtex2pro, I need to write an IP-component, that recive data from portpins and can transfer data to RAM directly. I'm tring to understand DMA, generated by...
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16 years ago
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sysace and high capacity CF
Hi All, I'm planning to attach a high capacity compact flash card to my Spartan-3 design. I don't want to use any file system on it, just raw data access. Is there any size limitation on the compact...
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16 years ago
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