Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
external clock frequency doubles
Hi People, I am attempting to interface the Xilinx Virtex - II Pro FPGA with a quad channel codec. I am using XC2VP30-FF896 FPGA on the Xilinx University Program Development Board.I had applied a...
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EDK 8.1i to EDK 9.1i UCF file errors
Hello, In our *working* EDK 8.1i project, we locked a DCM in the following manner in the UCF file (located in /data/system.ucf): INST dcm_sys/dcm_sys/DCM_INST LOC = DCM_X0Y0; INST...
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How do I constraint multiple clock cycle in Altera?
Hello everybody, My Altera design uses multiple clock cycle and negative clock edge, how do I constraint it? Here is my code, absolute_addr is generated 1.5 clocks earlier before consumption. I am...
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How to insert tab in Write() function in VHDL
Hi, I want to insert tab in write() function in VHDL. Here is a write() function definition: procedure WRITE(L : inout LINE; VALUE : in character; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0);...
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Quartus 7.1 Simulations
I have a strange issue with Quartus 7.1 simulation. I have a project with inputs a, b, c, and d. If I include inputs a,b and d in the .vwf file, the project will simulate in functional mode, but will...
 
I need advice
Hi all, I will be dealing with two fpga projects for school ; instructer has given some specs about these projects Could someone please give me some advice on choosing adequate fpga boards for these...
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Single Chip MSX computer full schematic and VHDL sources
Hi there is the distribution archive for the one chip MSX project would be fun to convert it for some xilinx board, :) I have been hunting for those VHDL code for ages, all links ended dead somewhere,...
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Precision RTL and DesignWare libraries
Hi, I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow? I am especially interested in the automatic conversion of DW RAM devices to...
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Xilinx Timing Constraint Questions
I need some help making sure I constrain a design properly. The input clock to the front end logic runs at 312 MHz. This is input to a DCM that produces clocks on CLK0, CLK90, and CLKDV (div by 8). I...
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How to port simulink design to FPGA?
Hi, I have a design where I have implemented a simple band pass filter found to be working even on hardware in the loop cosimulation. Now i have a problem since i am pretty new to simulink, I do not...
 
video soltion provider
Hello, Is there any expert who can guide me about the following problem: I need video system with following main specifications. 1) Input : standard video formats 2) compression: MPEG4/MPEG2 etc. 3)...
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Mobile DDR vs DDR2
Hi Folks, I need to put in DDR or DD2 interfaces. I need about 1.2GB/s bandwidth. As I am targetting a low end fpga, I am limited by the max bitrate on the i/o. (DDR333 or DDR2-400). What will be a...
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FPGA and LEGO Mindstroms
Two Students at TU Vienna (Alexander and Peter) have designed and built a very nice board to interface an FPGA (running JOP) with the LEGO Mindstorms system. Take a look at and also check their web...
 
Unusual question about generic port use (optional ports??)
Hi all ... I have been writing VHDL for many years now, but can't seem to figure something out. I'm writing a component called "cell" (no it has nothing to do with the cell processor). Since there are...
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Semaphores in xilkernel?
Hi, my name is Pablo and I have problems with the use of semaphores in xilkernel. I have created a struct based on pthread_t types, semaphores,... That is, I create a "mypthread_T" which is based on a...