Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Help: Best use of DCM in Spartan-3A?
For my design I must use two DCMs in series. How do I best use the CLKIN, RST, CLKFX and the LOCKED pin of the DCM? Should i AND togheter the CLKFX and LOCKED before connecting it to the CLKIN of the...
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16 years ago
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what is register packing?
I am reading Cyclone II device handbook. A concept, register packing confuses me. I know if we use the LUT and register in a Logic Element t implement unrelated function we call that is a register...
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16 years ago
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Inverse of a matrix
Hi all, Can anyone suggest simple algorithms for implementation of finding the inverse of a matrix (4 X 4)? Even information of IP Cores for such functionality will be greatly appreciated. Thanks in...
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16 years ago
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FIR Filter ON FPGA
Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish --> The FIR Filter coefficients are generated on a host system using LabView, these coefficients...
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16 years ago
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Re: Docs on s/w interfacing EDK based design
Unless I misunderstand the question: #include uint32_t addr = 0x00001234; // some address you want to access uint8_t *ptr = (uint8_t *) addr; foo = *ptr; // read a byte at ptr *ptr = 0xaa; // write a...
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16 years ago
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spartan-iie
I recently built a prototype using a xilinx spartan-iie specifically the xc2s150e-fgg456 which is programmed with an xcf02s prom. I have the prom connected first in the jtag chain. I am unable to...
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16 years ago
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Xilinx Seminars in Wiesbaden, Berlin, Hannover
Hmm, so many locations in Germany... Amsterdam is a much better choice :-) -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op
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16 years ago
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Xilinx Coregen 2.3 problem
Hi, We are using FIFO in our design. The FIFO has been generated using CoreGenerator 2.3. The programmable flags have been enabled. The threshold values have been kept within the depth limit. However,...
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16 years ago
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Linux device driver for FPGA Xilinx Virtex-4
Hi, I'm finding a linux device driver for FPGA Xilinx Virtex-4, somebody can help me? thanks.
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16 years ago
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Microchip ICD on FPGA
Hi, I want to implant a ICD into my Spartan 3 dev board. I need to program some Microchip PICs, and I wondered if I could use the FPGA, instead of buying an ICD board. Has someone already seen that ?...
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16 years ago
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How to calculate IFFT based on FFT result?
Dear All, I just wonder if there is a simple way to calculate IFFT based on FFT results? I was trying to configure xilinx FFT coregen v3.1 to perform IFFT operation, but no matter how hard I tried,...
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16 years ago
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PacoBlaze 2.2
Dear group: PacoBlaze 2.2 has been released. This version solves some bugs that were still lurking in the stack and interrupt manipulation. The cores have also received more testing, and more debug...
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16 years ago
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comp.arch.fpga :How to implement a 128-bit input CRC module in V5
Can I use the CRC hardcores in Virtex5 to implement a 128-bit input CRC module? and how? Thanks a lot.
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16 years ago
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Rodney Smith, long term Altera CEO, dies in accident
"Rodney Smith, a sports-car loving executive who built a startup programmable-logic company called Altera into an industry powerhouse, was killed Friday in a bicycle accident in Menlo Park. Smith, who...
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16 years ago
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Quartus-II 7.1 Systemverilog interface?
I've tried using the "interface" construct in a Quartus-II project, but I can't tell if it's working the way it is supposed to. I tried declaring an interface like the following: interface...
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16 years ago
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