Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: data compression algorithms on FPGA
Did someone have a realistic gate count for jbig on an fgpa?
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16 years ago
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Reg:Clock to pad Delay of the System Clock.
Hi experts, Hi all i need a help,I am using the spartan FPGA.I am using the DCM to scale the input clock frequency to clock signal is feed to the sram in the board,which is also the system cock.When i...
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16 years ago
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asynchronous circuit design
is anybody here who can guide me about asynchronous CAD tools. is any such CAD tool available. which asynchronous design methodology is used help me.
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16 years ago
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Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
Is it possible to install two diferent versions of EDK/ISE, that is, one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the first one for simulink, but my custom board uses the second...
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16 years ago
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XILINX IPCore
Hello, I recently bought a board that has a firewire port that uses PCI32 as a communication to the TI Link layer chip. I was told that I could easily communicate with the board by FPGA using Xilinx...
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16 years ago
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How to find a false path in the design
Hi Guys We have been knowing the false path and its nature but i am confused as to how to identify a false path in a design having say 100 modules. We know that false path as defination that it is the...
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16 years ago
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How to Find false path in a design
Hi Guys We have been knowing the false path and its nature but i am confused as to how to identify a false path in a design having say 100 modules. We know that false path as defination that it is the...
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16 years ago
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Weird! sysace_fwrite() cannot be found!!!???
Hi everyone, I run into a weird erorr. sysace_fwrite() cannot be found. --------------------------------------------------------------------------- undefined reference to `sysace_fwrite' collect2: ld...
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16 years ago
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Difference between DCM and PMCD
Hi, I will appreciate if someone clarify for me the difference between DCM and PMCD. When do you need to use both together (cascaded)? Thanks, Ahmed
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16 years ago
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svf file programming issue
I am using spartan3 XC3S400FG456C-4 device. For the past two years or so I have been creating the svf file and I am suddenly having some problem with the svf file. Basaically the software gives SDR...
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16 years ago
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Virtex4 CLKX2 DCM Jitter
I guess this is really one for Austin, but I wonder if anyone else has any input. My company supplys a design which is used in a V4LX25. The design uses external QDR SRAM @ 200MHz (400MBit). The...
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16 years ago
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Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
Hi, I have the following problem: I want to configure my virtex II pro with powerpc but when I try to download with JTAG the application doesn't run. So I have tried to use XMD, but when I init this...
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16 years ago
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Portable TCP/IP socket library
Anyone has a good pointer to a portable (Windows, *nix) TCP/IP socket library that can be used with VHDL FLI, Verilog PLI/VPI, SystemC, or SystemVerilog DPI? -- Amal
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16 years ago
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System Generator vs Synplify DSP vs Simulink HDL Coder
Hi, I'm looking for thoughts, impressions, pros, cons, etc, on System Generator, Synplify DSP, and Simulink HDL Coder. We develop image processing algorithms and we are trying to shorten the design...
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16 years ago
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Build error for multiprocessor sytem.
Hi, My basic version of design has two interconnected microblaze, FSL has been used for interconnection. There is one application on each microblaze such that frist writes to second then the second...
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16 years ago
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