Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
ANNOUNCE: Atom 2007.06
Atom is a high-level hardware description language embedded in Haskell that compiles conditional term rewriting systems into conventional HDL. New in this release: - User guided rule scheduling to...
 
Spartan3A-DSP Development Board
Once again we are producting some new development board products this time around the Spartan3A-DSP family. Given the positioning of this chip I would be interested in what you guys out there would...
 
xilinx windrv install on linux
Hi, since I want to start with my brand new xilinx Spartan 3e board on linux I followed the Answer Record #22648 for the linux 2.6.21 kernel and ISE9.1 at Compiling the debian kernel I followed one of...
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Affordable pcie card ?
I am after a pcie card where the ip doesn't cost an arm and a leg unlike that for xilinx's s3 pcie starter kit Got quoted > $15,000 for the pcie core(End point pipe) by the local distributor who was...
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linux and USB JTAG at Spartan 3e starter
Hi, I have here my brand new Spartan 3e starter kit, therefore I could test my vhdl code in real, could ... Anyway, I'm using ISE 9.1 Sp3 Webpack for Linux and from As mentioned in the README udev is...
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Another EDK Sim question...
Sorry about multiple posts, but I am just trying to migrate a project that was once working in sim over to 9.1 tools. I got all libraries compiled, EDK sim files generated, etc. By the way, the...
 
jaja
echt ofnie?
 
Newbie Question: Using Includes in Verilog
This is a very basic question. I would appreciate your help. I have a Xilinx FPGA Verilog project that containts several files. I would like to use an include file for some definitions that I would...
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PBGA FPGA in hi-rel application
Hi I am involved in a high reliability application where the device we want to use (Quicklogic EclipsePlus QL7160) is only available in a 208pin plastic PQFP (30mm sq) or 280pin plastic BGA (17mm sq)....
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Module LOCK possible in VHDL?
Dear I want to get "actual clock frequency" of my design (in ISE tool). Due to following problem, I am having trouble. I implemented 20-port "crossbar network" module, in which number of I/ O pins is...
 
FPGA with ARM+CAN+USB+ethernet+ADC
I wonder what that is? it looks like the product Triscend never announced, but maybe its a hoax, still funny at least the spec are known now what Triscend was about to announce just before it was...
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XST net splitting blocks placement
I have a Spartan 3 interfaced to a TigerSHARC via its "link port", which is a 4-bit wide DDR communications interface. The receive side of this interface on the FPGA consists of two 16x4 bit FIFOs...
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TimeQuest - clocks related by default?
Hi All, It is obviously my fault, and the correct answer is probably "RTFM" (1), but I've just lost significant amount of time, because TimeQuest treats clocks as related by default. The design which...
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Pin Capacitance Quartus 6.0
I have a warning with Quartus 6.0 software in the Fitter section. It says : "Found 71 ouput pins without output pin load capacitance assignment" In the "Device and Pin Options" I can see that in the...
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adaptive filter FPGA
thanks for looking and please help me. I have a 16 bit ADC sampling at 50Mhz. I take only 10 MSB and display i in my video 1024 x 768 as an output to check the signal. I see continuous line displayed...
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