Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
ON NEXT MONDAY : 17-JUNE-2006 Amontec will provide the ?how-to? program via a XILINX VIRTEX XC4VLX25 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! On next Monday, your Amontec JTAG...
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16 years ago
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how to speed up the write to the off chip ram
Hi, I have a core which generates 400+ parallel outputs per once. Each output can take only 3 possible values only: A,B,C [they can be coded in binary using only 2 bits]. I am looking to write these...
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16 years ago
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Virtex 4 Config
Hi Could someone just confirm for me that I can connect the config block t 3.3V in a Virtex 4 device. I have checked the data sheet and it seems t indicate this. I just want to check as I have been...
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16 years ago
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Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
Can I do this all in a FPGA? I would like to sync to an incoming pulse (its actually going to be a register write) that I will receive at approx 100hz, and generate a 8Khz output clock. This will be a...
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16 years ago
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Frogger and Scramble released
Pleased to announce the release of Frogger and Scramble (with source code) at Enjoy....
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16 years ago
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programming virtex2 FPGA
I have generated a .bit file and try to program xc2v3000 FPGA but through impact gives a message that checking done pin.............done pin do not high , program terminated. so i verify operation in...
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16 years ago
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KCAsm beta
Hello group. As some of you requested it, I have updated the KCAsm pico/pacoblaze assembler. The new version supports register aliases (really implemented as aliases for any kind of assembler...
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16 years ago
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Virtex 5 static and dynamic (re)configuration
Hi, Could someone explain me briefly which is the basic difference between static configuration and dynamic reconfiguration in Virtex5 ? Assuming I have to deal with the biggest Virtex5 device...
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16 years ago
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Stolen Spartan 3E-1600 Development Board
My apologies to those who'd consider this spam, but my house in Milpitas, CA was burglarized and among the less mainstream objects stolen were a Tektronix THS730 oscilloscope and a Digilent Spartan...
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16 years ago
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Virtex-4 pre-configuration pull-ups
I can't seem to find any data on the value of the "weak" pull-ups on the IO pins during configuration if the HSWAPEN pin is configured to give them. Does anyone know approximately what value the pull...
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16 years ago
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XIlinx tools question - how to quickly identify unconstrained paths
I trying to integrate an IP block from a client and it has a ton of clock crossing, most of which are probably OK. Up to now, I've run the Xilinx tools in an iterative mode - set constraints, run...
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16 years ago
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Programming Question
S/w used : Xilinx WebPack Chip : Spartan - XC2S200PQ208C I have configured a bus as a bi-direction by declaring it as 'inout' However on synthesizing the verilog files, the constraints editor shows...
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16 years ago
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TDM stream multiplex/demultiplex
Would anyone know if there is a core out there that can multiplex 4 2.048MHz TDM streams onto 1 8.192MHz stream? (and inverse). I'm having a hard time trying to write it on my own since I'm not that...
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16 years ago
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xilinx spartan3e kit ddr sdram
Hi all, is there any open source DDR SDRAM controller IP available (VHDL) for the DDR SDRAM on this kit ?
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16 years ago
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Apart from IEEE, is there some another journals for publishing an FPGA article?
Hi, I would like to know if someone could recommend me some journal for publishing my article about FPGA.
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16 years ago
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