Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Need help on clock forwarding on Xilinx Virtex-5
Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind...
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16 years ago
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help on clock fowarding between 2 FPGAs
Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind...
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16 years ago
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How to make a small (<4Kbyte) program for V4 PPC
I am trying to make a 4 Kbyte program to go in isocm at the top of PPC address space. It seems to build OK. But when I try to update the bitstream before downloading I get the somewhat cryptic error...
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16 years ago
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booting a large V4 PPC program with a minimum of on chip bram
I am trying to boot the PPC with a minimum of block ram, since I want to save that for my own hardware peripherals. My idea is to take the smallest amount of on chip memory (4K of isocm seems to be...
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16 years ago
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edk clock problem
Dear all, I am a graduate student at USF. I am working with XILINX XUPV2P board and i am using edk to interface memory and my RTL code (using import peripheral). the RTL code synthesizes at 70 Mhz and...
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16 years ago
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What is LatticeSC implementation of Virtex-4 ISERDES and OSERDES
Hi, For those who are familiar with Lattice/LatticeSC, what is LatticeSC implementation of Virtex-4 ISERDES and OSERDES (see Xilinx Application Note - xapp721) -young
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16 years ago
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Quartus Timing Analyzer question
Hi. I am working with Alera Quartus software on FPGA realization of STFT(Short Time Fourier Transform) and I have one problem. I am constantly getting this waring "Warning: Circuit may not operate....
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16 years ago
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Using LogicLock in Altera Quartus II
Hello, I'm looking for opinions on using LogicLock in Quartus II, is it useful or a waste of time? What are some of your experiences with LogicLock? thanks, joe
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16 years ago
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problems with FSL and Microblaze
I=B4m developing a FSL Peripheral. I=B4m having the following problem: when trying to generate the bitstream it generates the error: ERROR:MDT - issued from TCL procedure...
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16 years ago
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c code to initialize a peripheral
Hi everybody I am trying to familiar to xps software .So i am trying to create a peripheral using 2kb bram block in which we can read or write. I have written verilog code for a bram controller...
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16 years ago
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LogicSim v3.0 Verilog Simulator is Here!
LogicSim v3.0, an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification is finally here. This is a major release that contains many new features, updates and bug fixes....
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16 years ago
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ISE write permissions?
9.1 SP3 on XP. I can open my project from the "File" dialog, but if I try double-clicking the ISE file I get: "The project ... you are attempting to open does not have write permissions and therefore...
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16 years ago
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custom peripheral registers
Hi everybody, i' trying to realize a custom OPB peripheral using EDK. In my design I need a register in which one bit should be written by software and by the peripheral itself. Ok... I'll try to...
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16 years ago
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Incremental Compilation in Altera Quartus II version 7.1
Hello, I was wondering if anyone is using Incremental Compilation in Quartus 7.1 and if so, could you comment on it. Is it worth the time using IC or is doing Full Compilation better. In my current...
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16 years ago
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Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
This is not the first time I ask for this problem, but at the moment I go on trying to solve this problem. I have a custom board with a Micron memory. The company has said to me that I should use a...
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16 years ago
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