Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Tecis-Termin
Hast mich ganz sch=F6n geweckt heute morgen... wenn Du so lange snoozed und nicht raus kommst werd' ich wach. Ich hab' uns f=FCr Mittwoch 11.7. um 19:00 einen Termin mit Herrn Rolf Maier-Dammann...
 
how to assert PSEN for DCM
Hi all In the datasheet, psen has to be asserted before rising edge of psclk fo one clock. How can I implement this? Should I use the clock to driv psclk as the clock of my state machine? If so, then...
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Xpower complains about Vccint for Spartan 3A
I'm running into the following error message when I run Xpower on a Spartan 3A design: WARNING:Power:738 - Vccint not in recommended range [0.940..1.060]V. However from the datasheet DS529.pdf I see...
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How to simulate testbenches using the ISE simulator in linux
Hi guys.. A few days back I installed xilinx ISE webpack 91i on fedora core 6 everything worked out fine but i have not been able to simulate the testbench using the simulator provided by...
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Graduate/Junior FPGA Designer concerns
I have and odd question. As a final year student at EE course (thesis is a complex FPGA project) I am starting to get concerned about future job. I would like to ask, whether someone can present his...
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Help configuring XUP PPC for Ethernet
Hi everyone, We are a group of Computer Science students working on a project on the XUP board's PowerPC processor core to run an image processing algorithm and communicate back and forth with a PC...
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fitting problem on A54SX72A
Hi everyone, I have a strange behaviour in my implementation even if the design is pretty simple (even if it's very dense!). I have a decoding block which gets "address" to write data into several...
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anyone know a FPGA designer?
hi, I need to design and implement a very simple FPGA. There will be 34 TTL inputs. One (and only one) will be tripped every few seconds. I need the FPGA to report on which one was tripped. So the...
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How to measure clock fequency
Dear I am confused to obtain real "clock frequency" of my 2 implementations. Implementation details are following. In UCF file, (1) "CLK" is connected to Virtex-II Pro clock pin. (2) I constrained the...
 
EDK - Microblaze question
Is there a method of using external RAM (Generic external Memory) where the data, heap and stack can be located? Ideally the code would remain in BRAM so not to require additional external...
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Simulating analogue signal using ISE simulator
Hello all, Whenever I need to look at a filter output (or any DSP core), I used to define a real signal and assign it to what I want to examine, roughly something like this: dac_real_out
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ispLever 7.0
Evnin' Just received the download link for ispLever 7.0 and read the announcement... Is it really true that 7.0 supports now mixed Verilog/VHDL projects? And also that Synplify is included with the...
 
V4FX60, hard temac, MPMC2 and SoDIMM
Has anyone instantiated a MPMC2 interfaced to a SoDIMM and the following ports: 1) ISPLB (for the ppc405) 2) ISPLB (for the ppc405) 3) an OPB 4) a CDMAC for the hard temac When I try the build, if...
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V4FX and Microblaze 5.00.c hard multiplier not working
Has anyone run into an issue where the mult instructions return 0 when using the hard multiplier in the V4FX? BTW, I'm using EDK 8.2. Here's the snippet from my MHS for the microblaze instantiation:...
 
what is the correct way to capture ADC using fpga
Hi, can anyone tell me what is the correct way to capture data from 60 mh sampling, 16 bits ADC? Should I use 4 different phase shifte clock,0,90,180,270 with DCM and then decided which one work the...
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