Field-Programmable Gate Arrays - Page 64

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• 08-24-2007
• hwicap for EDK 9.1
• • Kevin
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• 0

• 
• 08-24-2007
• Dynamic power estimation using Xpower
• • mahshid
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• 2

• 
• 08-24-2007
• Samtec PowerPoser power filtering solution.
• • Symon
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• 4

• 
• 08-24-2007
• xilinx impact 9.2 problem
• • Rutger Stoots
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• 6

• -
• 08-24-2007
• OCM BRAM and PCC issues...
• • xenix
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• 0

• 
• 08-24-2007
• DDR2 controller V4 vs V5 differences ?
• • Sylvain Munaut
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• 6

• 
• 08-24-2007
• Speed test between FPGA and DSP or PC.
• • Pablo
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• 3

• -
• 08-24-2007
• Inout ports in EDK
• • Koustav
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• 0

• 
• 08-23-2007
• Annoying
• • Christian Obel
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• 1

• 
• 08-23-2007
• ROUTING=CLOSED in Xilinx 9.1 PR tools
• • jasuris
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• 2

• -
• 08-23-2007
• Altera DDR Controller, Modelsim and Verilog
• • fpgabuilder
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• 0

• -
• 08-23-2007
• ML365
• • maxascent
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• 0

• 
• 08-23-2007
• xilinx usb cable question
• • bert
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• 4

• 
• 08-23-2007
• comparison with embedded processor
• • bhb
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• 5

• 
• 08-23-2007
• how to bidirectional signal in xilinx EDK tool ?
• • kmk1978
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• 2

• 
• 08-23-2007
• Burst Memory Transfer Request from PPC
• • lordwolf
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• 1

• 
• 08-22-2007
• Power Reduction Strategy
• • tgschwind
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• 12

• 
• 08-22-2007
• Need to force all signals in a design to a known value at start of simulation
• • wittenjon
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• 9

• 
• 08-22-2007
• ML401 (Virtex 4 development board) as a USB peripheral
• • alleynb
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• 7

• 
• 08-21-2007
• help to sort out the errors
• • sriman
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• 2

• -
• 08-21-2007
• Call for Papers: RAAW-2
• • architect
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• 0

• 
• 08-21-2007
• MicroBlaze and ChipScope
• • icegray
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• 1

• 
• 08-21-2007
• System Generator Question: Flopping the inputs and outputs
• • Phil
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• 1

• 
• 08-21-2007
• Spartan-3A DSP vs. Cyclone III Power-wise
• • Manny
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• 7

• -
• 08-21-2007
• help on how to assign data to the function of nios program
• • sriman
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• 0

• -
• 08-21-2007
• FPL 2007 : Final call for participation
• • David Thomas
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• 0

• 
• 08-20-2007
• Old issues of XCell magazine
• • Peter Alfke
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• 2

• 
• 08-20-2007
• At what frequencies is it acceptable to generate a clock from a register?
• • bwilson79
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• 9

• 
• 08-20-2007
• exe file in modelsim
• • fazulu deen
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• 1

• 
• 08-20-2007
• Multiple MicroBlazes error
• • young
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• 1

• 
• 08-20-2007
• Voltage translation question
• • Eddie H
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• 14

• 
• 08-20-2007
• GPIO_performance
• • Vangelis
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• 2

• 
• 08-20-2007
• MCS -> BIT
• • LilacSkin
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• 4

• 
• 08-19-2007
• Globally Asynchronous in FPGA
• • Pasacco
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• 6

• 
• 08-19-2007
• Xilinx / ISE multi-cycle path constraint pitfall   [ 2 ]
• • eli.billauer
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• 23

• 
• 08-18-2007
• DDR controller - best device to perform
• • pgw
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• 16

• 
• 08-18-2007
• help on camera ports
• • sriman
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• 1

• 
• 08-18-2007
• Xilinx Constraints Question
• • moogyd
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• 4

• 
• 08-17-2007
• Minimal power?
• • amerdsp
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• 4

• 
• 08-17-2007
• Actel APA1000 and JTAG
• • Niv
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• 2

• 
• 08-17-2007
• Slice equation in bitstream
• • lembke.stefan
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• 14

• -
• 08-17-2007
• iMPACT command for selecting remote host running CableServer?
• • Marcel van de Burgwal
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• 0

• 
• 08-17-2007
• FIFO16 on virtex4 error?
• • Chao
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• 4

• 
• 08-16-2007
• Reconfiguring a Virtex4 DCM_ADV.
• • Symon
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• 2

• 
• 08-16-2007
• Routing JTAG pins thru FPGA
• • vu3rdd
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• 3

• 
• 08-16-2007
• FPGA :'define not allowed in ISE ?
• • bijoy
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• 1

• 
• 08-16-2007
• Scilab / Matrix
• • bhb
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• 1

• 
• 08-16-2007
• MGT Link
• • maxascent
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• 4

• 
• 08-16-2007
• synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
• • ankur
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• 1

• 
• 08-16-2007
• about mb-gcc error???
• • kobelai15
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• 3