Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Modelsim simulation Q
Sorry for this newbie-like question, but I can't remember how I did it before for the life of me. Normally I pre-select certain signals before I run the sim, and look at those in waves. The problem...
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Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
I know this topic has been already treated but at the moment I have no solution yet. Is it possible to edit this opencore so you could use internal feedback?.
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Achronix Async FPGA Silicon available when ?
I see Achronix and Mentor Graphics have inked a co-operation deal. Anyone know when their Async FPGA Silicon will actually ship ? -jg
 
Want to become part of Xilinx Applications Engineering ?
If you think you meet our high standards, and you would like to work in a challenging but friendly environment in San Jose, CA or Longmont, CO, then just e-mail me your resume. Might be the best move...
 
Can anyone identify the manufacturer of this Chip ?
I am interested in finding the manufacturer of U3 on this SSD device: The device in question is on the underside of the PCB above the letters "25SD". It has a strange Logo that I do not recognize. See...
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MIG 7.12 DDR2 bank availibility
I'm a MIG newbie and am trying to implement the following: Memory: DDR2, 64 MB x 16 x 2 chips (64 MB x 32 result) FPGA: XC4VLX25-10FF668 The DDR2 I/O requirements can be satisfied using one 'big' bank...
 
ML402 card (video starter kit) : Read/write on the ddr
Hello everybody, I am trying to make a software video processing with the VSK. For this, I want read video data from the DDR, applied the convolution algorithm and write the modified video data in the...
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Suggestions for Xilinx based evaluation board for image processing
Hello! I have been playing with image processing on FPGA for some time now, and the results seem interesting (I am working mainly on image preprocessing and edge/corner detection algorithms). My main...
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DFS to generate Frequencies slightly apart
Hello, for some legacy instrument, I need to replace AM796X Taxichips doing a 9B11B encoding/decoding. The Taxichip is long EOL, and replacement chips I know only do 8B10B or 10B 12B Data encoding can...
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How to use UART on Spartan 3E Starter Kit
Hello, Can anybody help me with some reference designs, through which I can get an insight to using UART on Spartan 3E Starter Kit ? I have downloaded few reference designs which uses UART but I am...
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Interesting problems about high performance computing
There is a software application which demonds huge computation. My aim is to port the software program into hardware. So first of all, I need to evaluate the required volumn of computation. The...
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[Announce] Linux 2.6.20 on MicroBlaze now available
Hi folks, Just a quick announcement that PetaLogix has released version 0.20 of our PetaLinux environment, which includes Linux kernel 2.6.20 support for MicroBlaze (2.4.31 kernel is also available...
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noisy rising edge clock - non-monotonic clock
We are having some tests failing under certain clock signals. The clock signal is generated in an external device with different drive strengths. The external clock is used to clock some Virtex2P...
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[ISE] how to synthesize XilinxProcessorIP/pcore
Dear I want to synthesize "opb_arbiter" in ISE. What I did was (1) Locate "opb_arbiter_v02_e" and "proc_utils_v1_00_a" (located in EDK directory) (2) Set up parameter : number of master = 4 (default)...
 
V4 PPC to sleep?
I want to put the PPC running linux in my virtex-4 to sleep to save power. Apparently, the official software suspend mechanism isn't supported/present in our kernel but the standard linux tree does...