Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Coding style of verilog for FPGA synthesis
hi, guys We design a hardware written in Verilog and synthesize by Synopsys Design Vision. The post-synthesis simulation is shown that the function of hardware is correct. Now, we are going to verify...
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16 years ago
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Confused about FPGA devices recommended by Xilinx for my FFT project
Hi everyone. I have selected spartan 3E family for an FFT project due to its low cost. The FFT core (v 4.0) specs say that for spartan3E devices, the footprint is as follows (see table) and they...
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16 years ago
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VGA 1080x1920 pixel chipset
Hi, I need a VGA 1080x1920 chip supporting HDTV. Anyone here has used before such IC ? thank you, Vasile
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16 years ago
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Can Cyclone II PLL_out be driven by the pll output c0 and c1?
As I know among the three outputs of pll(c0, c1, c2) only c2 can drive th dedicated PLL_OUT pin, but when in a design, when I assign the PLL1_OUT to c1, it can aslo works. Anyone know the reason?...
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16 years ago
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How to deal with RAM issue when generating blif
Hi, I am trying to generate a blif from verilog by using the command, quartus_map; however, there are some issues with RAM, so I can't get my blif. In the qsf_assignment_description.pdf, it has...
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16 years ago
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Xilinx FPGA: "after 10ns" constraint
I have some hard to debug issues in my FPGA image processing project: when I read the memory from the Virtex 4 chip at 15KHz rate (rather low). There are some undefined delays that are semi random:...
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16 years ago
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Interfacing expansion ports thru EDK
Hello everybody, I am trying interface to the J5 expansion port of the Digilent XUP2VP board through EDK. I read a previous post in the group and tried adding the following to the .xbd file for the...
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16 years ago
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Trouble using DCMs in EDK 8.2
I'm currently developing a design for the XUP development board. The development software is Xilinx EDk 8.2 The system requires several frequencies. Power PC : 100 MHz PLB : 50 MHz User IP : 50 MHz,...
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16 years ago
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Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM
I'm currently working on a design where there isn't an available GC pin to bring a clock in (bad design, not mine). It's an 80MHz single- ended clock, but the design requires an 80MHz and 120MHz...
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16 years ago
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How to choose FPGA for a huge computation?
I have post an topic serveral days ago, and there is the link. The total computation is described below: integer add 2442 Giga operations float add 814 Giga operations float substract 2424 Giga...
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16 years ago
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Control Panel application for Altera Cyclone II Starter Kit, help?
I'm using Altera's "Cyclone II Starter Kit", and while the board seems to work fine, I can't figure out one of the bundled utility programs. I installed the Cyclone II Starter Kit CD on my Windows/XP...
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16 years ago
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Desperate to find the right FPGA board
Hi guys. First post to this newsgroup, let's pop the champagne ;) I need your advice on selecting a FPGA module for my needs. Anyway. I need to stream data from a PC to a device, and back. Around...
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16 years ago
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Multidimensional Register in Modul Port List
Some of my modules implements a register bank controlled by CPU lines. Inside the module I use register banks, like reg [7:0] dac_sel[0:7]; However if I put these multidimensional register in the...
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16 years ago
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What wrong with the DCM of Virtex4 in my project?
I have built a EDK project to program an opb_pci bridge into a virtex4fx60 FPGA, in this design, a 100MHz clock from a crystal was the input for DCM, and a 2x ouput(200Mhz) was for the IDELAYCTRL...
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16 years ago
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IBIS Model V5 GTP output
As per my understanding V5 GTP support 1.2V CML standard. I downloaded the V5 IBIS model from Xilinx website but it does not seem to contain V5 GTP (1.2V cml) model. How can I get the 1.2V CLM IBIS...
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16 years ago
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