Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
I upgraded my Modelsim XE-III 6.2c starter edition to Modelsm XE-III 6.2g starter edition. Before isntalling the new software, I uninstalled 6.2c (from Control Panel), and then I deleted the...
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16 years ago
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Bit error counter - how to make it faster
My goal is to implement a bit-error counter targeting 1GHz. The datawidth is parametrizable. I started off this way, Verilog code: ---------- assign mismatch[datawidth-1:0] = input_data ^...
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16 years ago
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Bidirectional LVDS
I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with serial/ deserializer pairs at each end might work. Does anyone have any experience...
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16 years ago
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EDK Custom IP
I am trying to add a custom IP to my EDK project. I am using the Avnet Mini-Module (MM) and EDK 9.1i SP2. This is my first custom IP and I am starting off small. The MM baseboard has three LEDs that I...
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16 years ago
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VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with strong Verilog VHDL experience then we would like to...
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16 years ago
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Adding opb AC97 Controler in Xilinx EDK 8.2
Hi all, I am facing a problem. I cannot find the opb AC97 Controler in BSB, EDK 8.2 to add to my project. I am new to EDK Please some one help me out.... Thanking You cheers Dinesh
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16 years ago
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A strange error during PAR process in EDK, could anyone in xilinx help me?
The device is v4fx60-ES. EDK and ISE versions are 9.1.02 and 9.1.03 seprately. The error message apears as follows: Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 1 mins 10 secs Phase 8.8...
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16 years ago
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Virtex4 ISERDES question
I am simulating a verilog design that uses Virtx4 ISERDES primitive. This design requires the "O" ouput pin of the Virtx4 ISERDES primitive. The "O" pin in the Virtx4 ISERDES primitive provides a copy...
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16 years ago
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CameraLink to Hotlink-II video converter
Hi All, We are looking for a board (or adaptor) able to convert CameraLink video to Hotlink-II. Thanks in advance, Rotem
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16 years ago
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Can FPGAs inputs detect low currents?
Hello I'm new to FPGAs. I need some kind of 30-40 channel input extension beeing able to detect 0.01mA currents. (The current should flow through your fingrs .. ;) I already know that implementing...
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16 years ago
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regarding the montavista linux preview kit
Dear all, I am working on Virtex-4 Fx12LC (ML 403 ) Fpga that has powerpc hard core. I would want to load Linux RTOS onto it and try and access the on chip memory and Fpga logic from that. May I know...
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16 years ago
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Xilinx ISE 9.1 - Version Control - VSS
Greetings, Has anyone used Microsoft Visual Source Safe or any other software version control applications to manage ISE projects? More specifically what files are required to be maintained to keep a...
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16 years ago
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what is speed grade in virtes1
wht means speedgrade in xilinx fpgas? what rold speed grade plays in the design and selection of fpga for a design? If the speedgrade determines the delay etc..on wht basics they determine that. Plz...
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16 years ago
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Amontec chameleon
Hello Amontec, Larry, Spefically for you, since I did not get any reposone from the Amontec site! Could you explain the features of the chameleon. How does it work ? Can it be configured to work with...
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16 years ago
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Trace capturing
Hello, Im in embedded software development, but interested in developing a device which can caputure trace information from a Nexus class-3 compliant processor. Possibly later changed to capture trace...
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16 years ago
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