Field-Programmable Gate Arrays - Page 68

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• 07-24-2007
• Altera or Xilinx   [ 2 ]
• • Stef
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• 35

• 
• 07-24-2007
• Xint64 ?
• • Andrea05
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• 5

• 
• 07-24-2007
• tiny Spartan 3 module?
• • Eric Smith
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• 8

• 
• 07-24-2007
• Aldec ActiveHDL vs. ModelSim
• • spgoldman
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• 1

• -
• 07-24-2007
• Spurious NULs using uartlite
• • Philip Potter
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• 0

• 
• 07-24-2007
• 3 input adder in Spartan 3E
• • skyworld
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• 9

• 
• 07-24-2007
• Arming the Chipscope Pro ILA
• • Thomas Reinemann
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• 3

• 
• 07-24-2007
• hard_temac : mdio conflict
• • Paul
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• 9

• 
• 07-24-2007
• ise 9.2 fatal error
• • dude
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• 1

• 
• 07-24-2007
• Corgen Adder Vs DSP48 Adder in Virtex4
• • lkjrsy
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• 2

• 
• 07-24-2007
• Connecting Bram LMB Controller to Microblaze
• • mfgunes
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• 8

• 
• 07-23-2007
• VCD file doesn't show anything in GtkWave
• • Chris Carlen
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• 11

• 
• 07-23-2007
• Bizarre Xilinx configuration problem
• • Peter C. Wallace
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• 3

• 
• 07-23-2007
• DDR2 w/ MIG on Xilinx ML501 Board
• • bgelb.mit.edu
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• 4

• -
• 07-23-2007
• IOSTANDARD LVDS_25 Error after upgrade to ISE 9.2i
• • robquigley
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• 0

• 
• 07-23-2007
• On I2C protocol
• • devices
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• 15

• -
• 07-23-2007
• help: buggy IDE driver on Intel IXP425 GPIO(EXPB)
• • metiu
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• 0

• 
• 07-23-2007
• xilinx multichannel fir alignment
• • cpope
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• 3

• -
• 07-23-2007
• Could you explain the procedure about system simulation?
• • SangchulJung
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• 0

• 
• 07-23-2007
• FIFO Full logix - V4
• • motty
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• 2

• 
• 07-22-2007
• FPGA for HPC
• • bart.deboeck
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• 1

• 
• 07-22-2007
• watchdog timer: interrupt handler: microblaze
• • Aziz
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• 1

• 
• 07-21-2007
• FIFO : Synchronous WRITE, Asynchronous READ ?
• • Pasacco
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• 3

• -
• 07-21-2007
• how do Xilinx PCSPMA IP core detect presence of optical input?
• • water9580
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• 0

• 
• 07-20-2007
• Running Virtex5 GTP at lower data rate
• • Eddie H
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• 3

• 
• 07-20-2007
• Writing to bram and reading from bram with microblazer
• • mfgunes
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• 3

• 
• 07-20-2007
• Xilinx fpgas...
• • John Oyler
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• 7

• 
• 07-20-2007
• libero.actel. i need a clock in a non global pin.
• • merche
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• 1

• 
• 07-19-2007
• SDRAM vs DDR2 on Spartan3E
• • Guru
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• 1

• 
• 07-19-2007
• DDR2 vs SDR on Spartan3
• • Guru
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• 3

• 
• 07-19-2007
• Library unit VPKG is not available in library UNISIM
• • dhruvakshad
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• 1

• -
• 07-19-2007
• Using the EDK based video decoder
• • Koustav
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• 0

• 
• 07-19-2007
• Interfacing the EDK based video decoder
• • Koustav
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• 1

• 
• 07-19-2007
• Xilinx XST 9.2i.01 - still incomplete support for always @*
• • Xilinx User
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• 3

• -
• 07-19-2007
• Enterpoint Web Site
• • John Adair
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• 0

• 
• 07-19-2007
• modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
• • merche
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• 2

• -
• 07-19-2007
• libero.actel
• • merche
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• 0

• 
• 07-19-2007
• regarding specifying clock as internal signal in chipscope
• • ekavirsrikanth
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• 2

• 
• 07-19-2007
• JTAG detection
• • suruchi81
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• 1

• 
• 07-18-2007
• Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
• • Lue.Her
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• 14

• 
• 07-18-2007
• Can multiple Ferrite Beads be used to connect ...?   [ 2 ]
• • commone
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• 36

• 
• 07-18-2007
• BD file generation
• • fazulu deen
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• 3

• -
• 07-18-2007
• Actel. Libero. Synplify: "unbound component..."
• • merche
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• 0

• 
• 07-18-2007
• How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
• • Ssa
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• 1

• -
• 07-18-2007
• DDR SDRAM in extended military applications
• • fpgabuilder
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• 0

• 
• 07-18-2007
• Generating video noise.
• • Pete Fraser
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• 9

• 
• 07-17-2007
• 8B/10B decoding after serial transmission problem?
• • damc4
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• 2

• 
• 07-17-2007
• Actel. Libero. Synplify
• • dorama2
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• 3

• 
• 07-17-2007
• XC9572XL bus hold - Cant be disabled
• • Peter Wallace
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• 2

• 
• 07-17-2007
• BD
• • fazulu deen
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• 5