Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx programmer, many unknown devices...
I would like to ask some questions regarding a Xilinx JTAG programmer: First, it seems that the programmer doesn't actually connect to the LPT port because of gender mismatch. Luckily I have a...
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16 years ago
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Virtex5 LXT Clock Distribution
I am using four GTP transceivers of V5 LXT 110T FPGA. I used coregen to create the verilog output. When I looked at the verilog output, the 200MHz reference clock was fed to the GTP tile from the...
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16 years ago
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Interfacing a camera to a fpga
Hello everybody, I am trying to connect a 2 Meg pixel PixelPlus camera with a XUPV2P board based on Virtex 2P. The camera PCB has male connectors and tried connecting it using black tape. But when I...
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16 years ago
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Xilinx ngdbuild question
Hi, I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get .ngc. How do I specify this in ngdbuild command line? I tried to use " -l ", but I got the following error ERROR:NgdBuild:604...
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16 years ago
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Latches
This document is formatted in Rich Text (html). It contains a couple of images (ascii art). If you read it as plain text you are not able to see the images which require monospaced fonts (terminal).
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16 years ago
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How to snoop an inout signal in EDK?
For example, signal A is an inout signal of certain IP and connected to an external pin of the FPGA with a net(let's call it net_A). What I want to do is to add another pin just for output, and...
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16 years ago
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Execute from SPI flash
Execute from SPI flash has always appealed as one way to reduce the PCB cost of the Code memory needed by Soft CPUs. Winbond have had Double rate SPI devices at 150MBd, and I see they plan to release...
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16 years ago
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modelsim search path
Does any one know how to set the search path so my modelsim pe 6.0c will find the .mif file associated with my coregen blocks? I get the following error: # Loading C:/Xilinx/vhdl/mti_pe/ # ** Error:...
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16 years ago
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d-link router?
Does anyone know which cpu do they use in the d-link router/adsl modem dsl-g624t ? Aparently, they are running linux inside. How did they do that, scaling down the whole thing into only what they...
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16 years ago
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vista 64 bits
hi Xilinx, i had a look at ISE 9.2 today. It's supporting Vista 32 bits. When should we have a Vista 64 bits support ? regards
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16 years ago
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USB JTAG Programming
I'm looking at adding an embedded USB JTAG programmer onto our latest board, and am just looking for a bit of advice. The board has on it an Spartan 3, and an XCF08P Platform Flash prom, the main...
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16 years ago
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How to write constraints with a clock enable?
Hello, lets take this verilog example snipplet reg clk_en; reg [:0] wide_reg; always @(posedge clk) begin clk_en
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16 years ago
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ISE 9.1 Problem
Hi Can anyone tell me what Xilinx have done to the timing summary in ISE 9.1 In 8.2 it used to give you what you requested and by how much it was met In 9.1 it has changed with reference to MAXDELAY...
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16 years ago
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Analogue like signal interaction within cpld possible ????
Gents, please allow me to confront you with some strange timing behaviour which I have measured with an Xilinx XC95108 cpld. Consider two well conditioned clock signals of 10 MHz (both having EXACTLY...
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16 years ago
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Xilinx FPGA to interface to special I/O
I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at...
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16 years ago
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