Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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question about xilinx jtag
My socket seems not to be in the documentation. It looks a bit like those sockets of harddisk cables expect there are just 2 rows of 8. Is this jtag? Where is vdd/gnd/tdi/tdo/tck/tms Which document ?
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16 years ago
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Xilinx PCI Express solutions
Hi All, does anybody has any experience with the Xilinx Philips PX1011A solutions? Thanks in advance, Francesco
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16 years ago
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high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
After some search on this group, at the internet and at Xilinx web site I have not found a conclusive set of informations regarding the behavior of a Spartan-3's input pin in a high voltage signaling....
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16 years ago
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cosimulation
I am prototyping a IP core which was written in verilog languge in cyclone II application engineer wrote code in C for application i simulate the both in cadence simulation environment so that i can...
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16 years ago
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Can I use chipscoe to look at V5 GTPoutputs
I would like to know if I can use Chipscope to look at the V5 GTP outputs. I am using 4 GTP outputs at 3.125 Gbps and wanted to study the timing of it
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16 years ago
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Choosing the EPC16 or the EPCS64 for Stratix II
Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the Stratix II EP2S601020C3 on my board. Can any comment which method is better/faster? Altera's development kits are using the EPCS64...
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16 years ago
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About the parallel port jtag programmer,
About the parallel port jtag programmer, can anyone say what is the reason we require resistors at the inputs to the buffers. I thought buffers have high input resistance anyway?
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16 years ago
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Xilinx ISE + Multi CPU setup?
Does Xilinx ISE benefit from Multi CPU setups? Like offered by AMD Athlon64 X2, AMD Opteron, Intel Core2Duo etc..? Also would AMD AM2 socket + 800MHz DDR2 be really benefitial compared to non DDR2...
5
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16 years ago
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32bit multiplication in a PowerPC405 of a VirtexIIPro
Hello, I would like to do a 32bit multiplication. The result must be stored in a "64bitregister". I did that : Xuint32 test1=0xFFFFFFFF; Xuint32 test2=0xBBBBBBBB; Xuint64 *res64; res64 ->Upper =...
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16 years ago
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s3a kit - Use sma as signal output ?
Is it possible to use the sma connector on the s3a or s3e boards as a signal output not just a clock output ? I haven't properly used a dcm yet (only a few very basic designs) so I'm not sure if this...
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16 years ago
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Question about xilinx programmer
In the xilinx programmer diagram (jtag/parallel download cable) (0380507) there is note number 2 which tells us that d6 busy and pe are connected at the db25 end of data cable. What does that mean?...
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16 years ago
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intermitent boot in V4
I have an SOC design built in EDK 8.2.03 for a v4fx12. The fpga boots from an xcf08p serial prom. I have an intermittent problem that seems to come and go with every rebuild. What happens is the chip...
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16 years ago
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Multiplier in Xilinx
I have a problem about the data width of the output of multiplier. I am using the coregen Multiplier in Xilinx. a : std_logic_vector(3 downto 0); b : std_logic_vector(15 downto 0); q:...
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16 years ago
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Why PLL and not DCM for V5?
I would like to know why the coregen software uses the PLL to generate the two user clocks - one for the GTP and one for the fpga fabric? There are very limited number of PLLs so why not use the DLL...
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16 years ago
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How to pass several commands inside xps from script?
Does somebody know how to execute (pass) several commands inside xps? Now I invoke xps from a batch file through xps -nw project_dirsystem.xmp Then I would like to execute several commands and to exit...
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16 years ago
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