Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
Well it's not new at all, but I've just discovered Yet Another Open Source RISC core -- Lattice's Mico32. It comes with GNU tool-chain (making the software-development side similar to OpenRisc 1200?)...
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SystemC in modeling HW/SW
Hi, I was told by a friend that SystemC is currently the best to modeling hw/sw design. I've read on the internet where people were saying that SystemC is a more "complete model" which I don't quite...
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lpm_constant function in Altera Quartus 7.1
Hi. Is it buggy again, while using 32-bit hexdecimal number where most significant bit is one? What is the simplest workaround of this?
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EDK and ecncrpted .bit, .nky, .mcs files
I'm using EDK to try and produce a produce an encrypted bit file and using Impact an encrypted mcs file. I've looked at the literature but can't find anything about how to do this within EDK. Can...
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ISE 9.1i - Process Map Fail without any Error messages
I am using ISE 9.1i. I am getting an error in the Map process which says " Process MAP Fail" without showing any errors. There happens to be bug which was solved in 8.2i Service Pack 1, but still I am...
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Virtex-II Pro Flip-Flop Setup time
Hi, For our VHDL design, we are using an evaluation board that has a Xilinx Virtex-II Pro chip on it. The design calls for sampling of a digital signal at 100MHZ. The problem is that the signal...
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slave serial configuration of Vertex FPGA using a microcontroller
hi I want to configure a vertex FPGA using a PIC microcontroller in the slave serial mode . I am simply doing the following steps while configuring. 1.Hold prog_b pin low for some time to clear the...
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configuring vertex4 FPGA
hi i want to configure a XC4 series of vertex 4 FPGA using a micro controller. which bitgen file is to be ussed for default configuration. Is a title declaration generation for the verterx bitgen...
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DDR SDRAM simulation model, ML300, Infineon
Hello all, I m working on an application using DDR SDRAM and i want to simulate (timing simulation) the DDR SDRAM working along with the module i have created. the DDR SDRAM which is implemented on my...
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Synplify Problem
I am using Synplicity Synplify Premiere 8.8 and I ran into the problem that it keeps retiming my designs such that a great deal of the logic is placed before the input registers and/or after the...
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A Way for a DSP to tell an FPGA to load itself from Flash
Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP load itself from flash but after it's done loading, I would like the DSP to tell...
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Problem usign xilfatfs...
I'm trying to get some files of the CF in a XUP board with a VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with xilfatfs library. When I compile the libraries I get the next error: Running...
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Error message in ModelSIM PE
Does anyone know what the following error in ModelSIM means? # Loading work.dsss_modem_cosim(structural) # Loading # ** Error: bad arg: "48522 # Executing ONERROR command at macro ./ line 128 Below...
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regarding post place and route timing simulation steps........
hi all, i wanted to do the post place and route timing simulation in modelsim. i have got the files form the xilinx ise and i copied both * and *_timesim.vho file into the RTL folder for my...
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Spartan3A : timing Constraints / DCM Outputs
Hi Folks, have the following problem and couldn't found out yet how to solve it: I have a clock input CLK_A and a DCM. I use CLKO and CLKFX outputs of DCM. CLKFX is configured for 4X CLK_A. I define...
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