Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
Hello, I have build a system consisting of two Microblazes connected with an FSL channel. When using the putfsl_interruptable() macro data gets lost. If the FSL FIFO is full sometimes...
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16 years ago
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Timing in Modelsim
Hello, I'm trying to simulate my design in modelsim and i'm trying to find out if it is possible to choose the set_up delays of the clock signals in a simulation. Indeed in my simulation the clock...
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16 years ago
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QuartusII Web Edition software question
Hi All, I am new to Quartus II, and am trying to run a functional simulation. I am using the "Vector Waveform Editor" and put in input nodes and some of the output nodes that I want to see. However,...
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16 years ago
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QDR II SRAM Interface
Hi I am currently designing a circuit with a Virtex 4 FX FPGA and QDR I memory chip operating at 250MHz. I have a couple of questions :- 1) Can someone give me some advice regarding the decoupling...
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16 years ago
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spartan-3e idcode
Hi all, I've recently built a prototype board using a xilinx xc3s250e- ft256. The idcode read back through jtag is not recognized and has a different manufacturer, i believe it to be corrupt. The code...
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16 years ago
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[ISE] How to create and map user library in command-line?
Dear I need to "make a script (or batch file) for ISE tool" in order to "crate and map" user libraries". My VHDL code looks like following :...
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16 years ago
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DCM CLK driving load problem
hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i have two sub modules and a top module. i need to use DCM in all the 3 modules (2...
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16 years ago
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Which embedded O/S for a 32-bit RISC microcontroller?
My company may soon have to put together our first embedded system. Since we're beginners, we're probably not going to (a) know what we're doing, (b) have a good firm set of application requirements,...
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16 years ago
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Image Resolution Rescaling
Hello, I have to do some video scaling on 24-bit video for a 8-bit video dac and am looking for some help in scaling the data. The video image is 512 x 512 and each pixel is 24-bits. The video DAC is...
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16 years ago
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What is the resistance of a big FPGA for VCCINT (unpowered)
I've just got a brand new board with a Stratix II S180 on it. Before I power it on, I checked the power supply rails for short-circuits. I get 20 ohms on the 1.8V supply rail and 1.2 Ohms for the...
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16 years ago
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Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
My setup has two Xilinx FPGA's which communicate with one another through two unidirectional system-synchronous interfaces. FPGA 1 is an XC2V3000-FF1152-4 and FPGA 2 is an XC4VLX160-FF1148-11. Both...
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16 years ago
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Newbie's first FPGA board !
Hello, I have used a FPGA module, XPS, microblaze, verilog etc for a personal project. This was very interesting and now, I am trying to design my own FPGA mini board. This is also a learning...
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16 years ago
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Xilinx V4 Custom IP
I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a custom IP to prove to myself I am doing it correctly instead...
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16 years ago
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Counter ?
Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop counting when reached max or rollover; will restart counting only after a total reset,...
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16 years ago
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Re: highly-parallel highspeed connection between two FPGA boards
That is an astonishingly high data rate (~70 Gbps to ~150 Gbps)! I won' ask what it's for, as I suspect you wouldn't be able to tell us. ;-) How far is the system architecture defined? Instead of a...
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16 years ago
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