Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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On I2C protocol
As for the I2C Master, assuming no clock stretching is issued by the Slave, here is a common situation and its concerning counterparts. Usual scenario: 1) Start - b1 - b2 - Stop And relative...
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16 years ago
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help: buggy IDE driver on Intel IXP425 GPIO(EXPB)
I have to use this ide vhdl driver that's supposed to link an IDE channel to the expansion bus of an IXP425 Intel processor. I asked why they didn't just connect the IDE signals to the GPIO, but they...
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16 years ago
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xilinx multichannel fir alignment
I'm using the v5.1 coregen fir, decimate by 2, two channel operation to process my I/Q. My system clock is 56 Mhz and the I/Q data rate is 500 ksps so I'm sure the latency is okay for the single dsp48...
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16 years ago
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Could you explain the procedure about system simulation?
Hi I'm studying Embedded system using XUPVP2PRO and use the tools ISE 8.1, EDK 8.1 and ModelSim 6.0 SE. I want to verify my custom IP. so I found the manual ( it was based on ISE 8.2 and EDK 8.2. So...
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16 years ago
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FIFO Full logix - V4
I am working with a dual port RAM FIFO module that has a 32-bit write port and an 8-bit read port using asynchronous clocks. The full and empty flags use static thresholds...meaning I didn't choose...
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16 years ago
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FPGA for HPC
Dear, I'd like to learn programming FPGAs for HPC applications. I am, however, a newbie in this field. I do have a software engineering background. Does anyone want to be so kind to suggest a...
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16 years ago
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watchdog timer: interrupt handler: microblaze
I have been trying to write a watchdog interrupt handler and have not been successful in coming up with a working code. I would like to use watch-dog timer on OPB bus of microblaze system to count the...
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16 years ago
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FIFO : Synchronous WRITE, Asynchronous READ ?
Dear Using BRAM (for example, RAMB16_S36_S36), I do need to implement "synchronous WRITE, asynchronous READ" FIFO. I still do not get to solution. My FIFO module has following I/O....
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16 years ago
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how do Xilinx PCSPMA IP core detect presence of optical input?
I use Xilinx PCSPMA GTP IP core to connect SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core to indicate presence of optical input?
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16 years ago
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Running Virtex5 GTP at lower data rate
At power-up, I need to run the Virtex GTP at 400Mbps and then after the initialization, I need to run the V5 GTP at 3.2 Gbps. In order to keep it simple, I am thinking about running the V5 GTP at 3.2...
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16 years ago
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Writing to bram and reading from bram with microblazer
Hello, I am a newbie in microblaze.I'm trying to implement a basic data readin and writing to bram with you help me where can i find basi tutorials about that.(more useful tutorials than xilinx page:)...
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16 years ago
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Xilinx fpgas...
I've been looking at the Spartan 3an's mostly, because of the built-in config flash, but I've yet to settle on them as the preferred chip for my project. As it turns out, another chip I'm wanting to...
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16 years ago
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libero.actel. i need a clock in a non global pin.
Is possible force the assignation of a clock to a pin (non global pin)? (=BFcan i do before synthesize?) On synthesis the clock is put in a global pin, and after that, on compilation, on layout I...
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16 years ago
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SDRAM vs DDR2 on Spartan3E
Hi all, I am considering to replace a SDRAM with a DDR2 on a custom Spartan3E1200 board to gain some bandwidth in a Microblaze system. Currently I am working with OPB_SDRAM core and I am not satisfied...
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16 years ago
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DDR2 vs SDR on Spartan3
Hi to all, I am considering to replace the x16 SDRAM for a x16 DDR2 to gain some bandwidth for a MicroBlaze system. I wonder if someone tested the Xilinx EDK MCH_OPB_DDR2 memory controller core for...
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16 years ago
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