Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Question about GSR?
Hello, What does GSR pin do, when should I use it? How do I use it? Is it required in every design? Thanks in advance for any response.
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V5 Differential Select I/O
Xilinx V5 supports Differential select I/O data rate upto 1250 Mbps. It supports HT_25, LVDS_25 and may other electrical standards. What electrical standard should be used to support the maximum...
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Xilinx XC3S400-4PQ208C pin name files?
Where on does one find those files with pinname files? Like this: 1 GND 2 IO_7 207 PROG_B 208 TDI etc.. I know this was brought up before, but finding the thread.. in the usenet haystack ;)
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Can Xilinx and Altera be on the same JTAG chain for programming?
If I put a Xilinx SysAce and two Altera Stratix II FPGAs on the same JTAG chain, will I be able to program the two Altera parts with Quartus and the SysAce with impact? If so, will it work as it...
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doubts
Hai all, I am having the following questions in SDIO : Which register will decide the mode as DMA or Normal mode? Wat does command with response with no data mean?wat does it do?can u give some...
 
regarding the post PnR timing simulation.....
hi all, i have done the post place and route timing simulation for my design. i am getting the following warnings . there is a setup time voilation but can any one explain what this statment means...
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completely open source fpga toolchain
Please bear in mind that this is only an 8-bit ripple-carry adder, and the tools are still quite crude, but I believe we now have the first-ever instance of a design being taken through a 100%...
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MS 6.2 code coverage report
Hi, I am facing a strenge problem in using Model Sim 6.2 code coverage report generation CLI. e.g. I have a modular design, as shown: device | |_ top | |_ H1 | |_ H2.1 |_ H2.2 | |_ H3.1 |_ H3.2 |_...
 
X values in ASIC
Hi, I just overheard about a kind of standard lib component F/F, which are used to "smash" X-values at the module level boundary. This components are said to have a quality of either pushing "0" or...
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why my usb cable can established,but can't download??? xilinx
hi, all: i install ise9.1 in my gentoo linux. i connect usb cable and run the impact. it displayer the error information : Connecting to cable (Usb Port - USB21). Checking cable driver. File version...
 
Best CPU platform(s) for FPGA synthesis
OK, the questions apply primarily to FPGA synthesis (Altera Quartus fitter for StratixII and HardCopyII), but I'm interested in feedback regarding all EDA tools in general. Context: I'm suffering some...
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DCM with Xilinx Spartan 3E and Precision
Hello everyone, I would like to use an DCM in a Xilinx Spartan 3E device. The synthesis is done with Mentor Graphics Precision. So I created a verilog file with verilog, but when I run synthesis, I...
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Is my microblaze cache functioning?
Hello all, I am using a Spartan 2E 600-LC development board. When I created the project using the BSB I did not specify the use of caches. I am now trying to enable instruction and data caches. I did...
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plb_temac with lwip and sgdma
Hi, is there any documentation for using plb_temac and lwip with the DMA enabled in plb_temac ? Thank's. Paul.
 
Problem with X_FF primitive acting as a latch instead of a fliflop
Hi alls, I've a amazing problem in my virtex XC2V1000 design. I've verilog code which normaly should generate a D flipFlop with preload ( and it did in functional simulation): input [7:0] reset; input...
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