Field-Programmable Gate Arrays - Page 83

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• 04-12-2007
• spartan 3e availability
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• 04-12-2007
• SETUP & HOLD time confusion
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• 11

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• 04-12-2007
• XPS behavioral simulation fails: the design is not loaded
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• 4

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• 04-12-2007
• Problem with EDK 8.2 MicroBlaze Tutorial
• • Scott Willis
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• 04-12-2007
• Changing LUT input size in synthesize
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• 04-12-2007
• EDK + XMD
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• 04-12-2007
• how two sine signals are multiplied in VHDL language
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• 04-12-2007
• Which are the best books about CORDIC algorithms and applications
• • Weng Tianxiang
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• 15

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• 04-12-2007
• XST and Verilog $readmemh
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• 1

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• 04-12-2007
• Timing violations though constraints have been met
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• 3

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• 04-11-2007
• ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
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• 04-11-2007
• lwIP, temac, and DMA
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• 0

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• 04-11-2007
• POC at Element CXI
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• 2

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• 04-11-2007
• has anyone used mathstar field programmable object arrays?
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• 3

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• 04-11-2007
• Wanted: XUP Virtex II Pro DDR-controller
• • woutervh
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• 0

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• 04-11-2007
• Help!! FIR Polyphase second - order interpolator
• • kangwei365
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• 1

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• 04-11-2007
• FIFO newbie question
• • nezhate
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• 4

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• 04-11-2007
• Query in Parallel CRC(urgent)
• • osr
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• 2

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• 04-11-2007
• Please HELP: timing problems on Virtex-4FX
• • Dima
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• 04-11-2007
• Xilinx WebCase support
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• 7

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• 04-10-2007
• CPLD + µC with reasonably-priced tools?
• • H. Peter Anvin
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• 12

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• 04-10-2007
• Flip Flop problem (asynchronous or synchronous???? )
• • Amine.Miled
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• 3

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• 04-10-2007
• Problème de bascues (asynchrone ou synchrone?)
• • Amine.Miled
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• 2

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• 04-10-2007
• EDK 8.2 MicroBlaze Tutorial
• • Scott Willis
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• 0

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• 04-10-2007
• Available: Detailed RISC CPU IP Core Design Documentation
• • John Gulbrandsen
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• 0

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• 04-10-2007
• System Generator pcore I/O performance results
• • eejw
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• 7

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• 04-10-2007
• Ross Freeman - inventor of the FPGA
• • fancier.fpga
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• 5

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• 04-10-2007
• JTAG Tap Master (was: TI Tap Controller std8980)
• • Amal Khailtash
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• 04-10-2007
• website for chip designers
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• 2

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• 04-10-2007
• SetJmp/LongJmp for Microblaze
• • Pablo
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• 04-10-2007
• Newbie with bus width mismatch problem. Quartus II
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• 04-10-2007
• VIrtex-4 FIFO16
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• 04-10-2007
• C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred O...
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• 04-10-2007
• Why I cannot use the XAUI core(generated by xilinx)
• • mynewlifever
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• 04-10-2007
• is there any opensource alternatives to platformstudio and microblaze development?
• • CMOS
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• 4

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• 04-10-2007
• File open, read and write in Xilinx EDK 7.1
• • Andy
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• 0

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• 04-09-2007
• record type port in vhdl and simulation in ISE
• • mans
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• 2

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• 04-09-2007
• Modelsim Low and High violations
• • M. Hamed
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• 04-09-2007
• Word sync in Cypress FX2 fifos /w 8 bit bus
• • cs_posting
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• 8

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• 04-09-2007
• MGT Clocking
• • Matthew Hicks
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• 1

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• 04-09-2007
• Looking for Xilinx fpga board that works in Linux and has Ethernet card
• • Thuy Pham
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• 04-09-2007
• ByteBlaster Parallel Driver for Linux > 2.6.13
• • Jedi Router
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• 0

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• 04-09-2007
• Measuring the period of a signal
• • axr0284
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• 4

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• 04-09-2007
• Clocking data into a shift register on positive AND negative edges
• • Philip Pemberton
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• 6

• 
• 04-08-2007
• How do I use the Xilinx USB download cable for testing?
• • Pedro
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• 04-08-2007
• query
• • ram
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• 04-07-2007
• Xilinx ISE constanly asking to regenerate a core file.
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• 4

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• 04-07-2007
• raggedstone + xc3sprog?
• • Adam Megacz
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• 5

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• 04-07-2007
• A new way to define systems of systems?
• • Richard Pennington
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• 16

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• 04-07-2007
• ispLever FTP Download
• • Jedi Router
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